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The mechanism of memory window (MW) degradation of Hf0.5Zr0.5O2-based ferroelectric field-effect transistors (FeFETs) with program/erase (P/E) cycling is investigated. First, the P/E cycling properties of the FeFETs are characterized at different cycling voltages. Then, the midgap voltage method is proposed to address the underlying drivers for the threshold voltage shift and MW degradation by separating the effects of oxide-trapped charges and interface-trapped charges. The mechanism for different threshold voltage evolutions between programed and erased states during P/E cycling is revealed. Moreover, the amount of MW degradation is nearly equal to the difference of midgap voltage shift values between programed and erased states, and the interface trap generation contributes to the midgap voltage shift. [ABSTRACT FROM AUTHOR]

Effect of oxygen annealing on bipolar resistive switching (BRS) properties of TiN/ZnO/CeO 2-x /Pt devices was investigated. Bilayer ZnO/CeO 2-x thin films were fabricated by rf-magnetron sputtering. It was observed that the improvement in cycle-to-cycle endurance degradation and uniformity of the bilayer ZnO/CeO 2-x thin film is optimum at 400 °C annealing temperature due to decrease in oxygen vacancies during annealing, as confirmed by x-ray photoelectron spectroscopy. The BRS could be caused by the formation of interfacial TiON layer, which is most likely to be accountable for creating an adequate quantity of oxygen vacancies necessary for the formation and rupture of conductive filaments. Smaller Gibbs free energy of the formation of interfacial TiON ( − 611 k J m o l − 1 ) layer as compared to bilayer film ZnO ( − 650 k J m o l − 1 ) and CeO 2 ( − 1024 k J m o l − 1 ) results in an easier re-oxidation of the filaments through the oxygen exchange with TiN top electrode. The analysis of current–voltage characteristics shows that the charge transport mechanism is Schottky emission. Moreover, the temperature dependence of high resistance state (HRS) and low resistance state (LRS) revealed the physical origin of the RS mechanism, which entails the oxygen vacancies for the formation and rupture of conducting paths. [ABSTRACT FROM AUTHOR]

The endurance degradation mechanisms of p-channel floating gate flash memory device with two-transistor (2T) structure are investigated in detail in this work. With the help of charge pumping (CP) measurements and Sentaurus TCAD simulations, the damages in the drain overlap region along the tunnel oxide interface caused by band-to-band (BTB) tunneling programming and the damages in the channel region resulted from Fowler-Nordheim (FN) tunneling erasure are verified respectively. Furthermore, the lifetime model of endurance characteristic is extracted, which can extrapolate the endurance degradation tendency and predict the lifetime of the device. [ABSTRACT FROM AUTHOR]

Electrically Erasable Programmable Read Only Memory (EEPROM) is a widely used memory device, nowadays implemented in submicron technology nodes. In this paper we show how the well-known trapping power law found in the literature can be retrieved by combining well calibrated state of the art Technology Computer Aided-Design (TCAD) simulations with a compact model for tunnel oxide degradation during EEPROM cycling. We pinpoint how this approach can be used to predictively assess the programming window closure and consequently, considerably reduce the time-consuming cycling test procedure. Finally, we show how this methodology can cover a wide range of temperatures, making it very attractive for high demanding applications such as automotive. • TCAD simulation of a state of the art 110 nm technology node EEPROM cell. • Predictive simulation of the programming window closure. • Can be extended in a temperature range typical of automotive applications. • This approach is transposable to NAND Flash-EEPROM and possibly to NOR Flash-EEPROM. [ABSTRACT FROM AUTHOR]

Resistive random access memories (RRAM) have shown tremendous potential in replacing Flash technology for future non-volatile data storage device applications in just about a couple of years from now. Although RRAM has various advantages in terms of simple design, high density integration and CMOS compatible process flow, it has its own intrinsic constraints in terms of variability and reliability, just as is the case for any other technology. While performance and reliability are both key metrics for any new product or technology design initiative, the critical aspect to investigate is the trade-off involved in improving them, as the measures implemented to boost performance do not necessarily have a positive impact on its reliability (lifetime). Optimization of the RRAM design for commercial applications requires a clear understanding and acknowledgment of these performance – reliability trade-offs. This study presents a qualitative perspective to identifying and understanding these trade-offs and probing the various sources of variability in high-κ RRAM. [ABSTRACT FROM AUTHOR]

In this paper the impact of the endurance degradation on the programming window and the energy consumption of flash floating gate memories is investigated. Using a new measurement technique we characterized the evolution of the dynamic drain current during the channel hot electron programming through the cycling. This experimental method has been developed for 90 nm technology node flash floating gate memories, but it is fully compatible with the highly scaled devices. We define the programming efficiency as a new figure of merit to evaluate the performances of flash memories and we demonstrate why this decreases during the cell aging. Moreover we confirm that the efficiency optimization point varies with the cell degradation. Finally, with a complete set of measurements, we show that our experimental protocol enables the understanding of the role of defects generation on the programming efficiency of NOR flash memories for embedded low energy applications. [ABSTRACT FROM AUTHOR]

As one key issue of resistive switching (RS) memory, the cycling endurance is poorly understood in hybrid perovskite‐based memory devices. Here, the cycling failure and the corresponding cycling‐induced degradation of CH3NH3PbI3‐based resistive random access memory devices are discussed. The high resistance state clearly decreases with the number of operation cycles, finally triggering irreversible failure in the collapse of switching window. By monitoring the I–V curves for all cycles, a negative set event is observed to be the critical turning point that considerably accelerates the cycling degradation rate. The decrease of |Vset| and |Vreset| indicates a reduction of the migration barrier of iodine vacancies (VI), which accounts for the appearance of a negative set after cycling. The understanding of RS cycling degradation can promote the optimization of device endurance by slowing the defect accumulation rate. The endurance degradation of CH3NH3PbI3‐based RRAM is attributed to the excessive defect accumulation during cycling operation. During the reset process, a negative set event is observed to accelerate the endurance degradation rate. Moreover, the decrease of transition voltages suggests a reduction of the migration barrier of iodine vacancies with cycling operation. [ABSTRACT FROM AUTHOR]