EEPROM endurance degradation at different temperatures: State of the art TCAD simulation.

Electrically Erasable Programmable Read Only Memory (EEPROM) is a widely used memory device, nowadays implemented in submicron technology nodes. In this paper we show how the well-known trapping power law found in the literature can be retrieved by combining well calibrated state of the art Technology Computer Aided-Design (TCAD) simulations with a compact model for tunnel oxide degradation during EEPROM cycling. We pinpoint how this approach can be used to predictively assess the programming window closure and consequently, considerably reduce the time-consuming cycling test procedure. Finally, we show how this methodology can cover a wide range of temperatures, making it very attractive for high demanding applications such as automotive. • TCAD simulation of a state of the art 110 nm technology node EEPROM cell. • Predictive simulation of the programming window closure. • Can be extended in a temperature range typical of automotive applications. • This approach is transposable to NAND Flash-EEPROM and possibly to NOR Flash-EEPROM. [ABSTRACT FROM AUTHOR]