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A hardware‐efficient slope‐error (SE) algorithm based four‐level pulse amplitude modulation (PAM4) baud rate clock and data recovery (CDR) scheme is proposed. The algorithm uses three adjacent data information to obtain slope information, thus reduces the required error samplers by 75% compared to the widely used baud rate CDR, namely, Mueller Müller (MM) CDR when working at same phase detector (PD) gain. The power efficiency of the CDR loop is improved by 36% compared to MM CDR. The proposed PAM4 baud rate CDR does not bring in extra block except for PD, which makes it easy to be extended from adaptive decision feedback equalisation. A 40 Gb/s PAM4 receiver with the proposed CDR is designed in 55 nm CMOS process. The simulated jitter tolerance of the CDR at high frequency exceeds the SONET OC‐768 JTOL mask by at least 0.35 UI at the bit error rate of 10−12. The CDR loop consumes 106 mW from a 1.2 V supply and occupies an active area of 0.1 mm2. [ABSTRACT FROM AUTHOR]

A compositionally step‐graded (CSG) InGaN barrier is designed for the active region of c‐plane blue light‐emitting diodes (LEDs). High external quantum efficiencies of 45, 42, 39 and 36% are achieved at current densities of 100, 200, 300 and 400 A/cm2, respectively. Compared with GaN barrier devices, LEDs with CSG InGaN barriers showed higher power, lower operating voltage and smaller wavelength blueshift, compared with GaN barrier LEDs. Owing to the low‐voltage performance, higher wall‐plug efficiency can be achieved for blue LEDs with CSG InGaN barriers. [ABSTRACT FROM AUTHOR]