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In this study, we proposed a pre-distorted driver of a power amplifier in which the driver stage can serve as a pre-distorter of the power stage. In order to secure the linearity of the power amplifier, AM-PM distortions according to the input power of the common-source (CS) and two stacked-FET structures were analyzed and compared with the simulated results. Based on the analyzed AM-PM distortions of the two structure, it was verified that the driver stage with CS structure can act as a pre-distorter of the power stage with the two stacked-FET structure by optimizing the bias voltages of the two structures. The Ka-band power amplifier was designed with a 65-nm CMOS process to verify the feasibility of the proposed pre-distorted driver stage. At 28 GHz, the measured P1dB, saturated output power (P $_{\mathrm {SAT}}$ ), and peak power-added efficiency (PAE) were 18.6 dBm, 19.7 dBm, and 32.9%, respectively. The measured small signal gain was 24.1 dB. When 5G-NR modulation signals (64-QAM, 100-Msym/s, 9.7-dB PAPR) were used, under conditions where the EVM was less than –25 dB, the measured output power and ACLR were 13.3 dBm and –29.4 dBc, respectively.

In this study, we propose a CMOS power amplifier (PA) using a bypass technique to enhance the efficiency in the low-power region. For the bypass structure, the common-gate (CG) transistor of the cascode structure of the driver stage is divided in two parallel branches. One of the CG transistors is designed to drive the power stage for high-power mode. The other CG transistor is designed to bypass the power stage for low-power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. The measured maximum output power is 20.35 dBm with a power added efficiency of 12.10%. At a measured output power of 11.52 dBm, the PAE is improved from 1.90% to 7.00% by bypassing the power stage. Based on the measurement results, we verified the functionality of the proposed bypass structure. [ABSTRACT FROM AUTHOR]

We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%. [ABSTRACT FROM AUTHOR]

ABSTRACT In this study, we analyze the effects of a power splitter on the output power and the power consumption of a CMOS power amplifier using a distributed active transformer as an output balun. On the basis of the analyzed results, we propose a split driver stage structure to mitigate the undesired effects of the conventional power splitter. In the proposed structure, the power splitter is located between the first and second driver stages to isolate the input node of the power stage from the parasitic components of the power splitter. To verify the feasibility of the proposed structure, we designed conventional and proposed 1.9-GHz CMOS power amplifiers using 0.11-µm RF CMOS technology. The measured efficiency and output power of the proposed amplifier are improved compared to those of the conventional amplifier. From the measured results, we successfully verify the feasibility of the proposed split driver stage structure. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2341-2345, 2014 [ABSTRACT FROM AUTHOR]

ABSTRACT This contribution presents the analysis, design and characterization of a high gain Doherty power amplifier implementing an integrated Driver stage in the Auxiliary branch. Guidelines and design equations are demonstrated, fulfilling the full integration of the whole new architecture. The development of a microwave monolithic integrated circuit prototype based on TriQuint GaN technology for 7 GHz applications is reported. 10.5 dB of Gain, 38.1 dBm of saturated output power and 42% of efficiency at 7 dB of output back-off have been demonstrated by experimental results. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:498-507, 2014. [ABSTRACT FROM AUTHOR]

ABSTRACT In this study, we design an X-band switching-mode CMOS power amplifier using 0.13-μm RF CMOS process. The power amplifier is composed of driver and power stages. In this study, we focus on the power consumption of the driver stage. To minimize power consumption, we propose a shot-through current rejection technique for the Class-D amplifier used as a driver stage of the CMOS power amplifier. We split the gate bias of the NMOS and PMOS of the Class-D amplifier using DC-blocking capacitors to control the shot-through current. From the measured results, we successfully prove the feasibility of the proposed technique. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1159-1162, 2014 [ABSTRACT FROM AUTHOR]

A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in a baseline 65 nm CMOS technology. The PA is constructed as a cascode stage formed by a standard thin-oxide device and a dedicated novel high voltage extended-drain thickoxide device. Both devices are implemented without using additional masks or processing steps. The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (P[subout]) and power back-off levels. At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off. Stress tests indicate the reliability of both the novel high voltage device and the design. [ABSTRACT FROM AUTHOR]

Abstract: This paper describes the design of a highly integrated ultrasound sensor where the piezoelectric ceramic transducer is used as the carrier for the driver electronics. Intended as one part in a complete portable, battery operated ultrasound sensor system, focus has been to achieve small size and low power consumption. An optimized ASIC driver stage is mounted directly on the piezoelectric transducer and connected using wire bond technology. The absence of wiring between driver and transducer provides excellent pulse control possibilities and eliminates the need for broad band matching networks. Estimates of the sensor power consumption are made based on the capacitive behavior of the piezoelectric transducer. System behavior and power consumption are simulated using SPICE models of the ultrasound transducer together with transistor level modelling of the driver stage. Measurements and simulations are presented of system power consumption and echo energy in a pulse echo setup. It is shown that the power consumption varies with the excitation pulse width, which also affects the received ultrasound energy in a pulse echo setup. The measured power consumption for a 16mm diameter 4.4MHz piezoelectric transducer varies between 95μW and 130μW at a repetition frequency of 1kHz. As a lower repetition frequency gives a linearly lower power consumption, very long battery operating times can be achieved. The measured results come very close to simulations as well as estimated ideal minimum power consumption. [Copyright &y& Elsevier]

This letter presents a two-stage quasi-class-E monolithic microwave integrated circuit power amplifier at 2.0GHz, which is based on field-plated GaN high electron mobility transistor technology. It consists of a driver stage and a power stage. The circuit schematic is described. The amplifier achieves an output power of 37.5dBm into a 50-Omega load, a power added efficiency (PAE) of 50%, and a gain of 18.2dB. A power density of 5.6W/mm is achieved [ABSTRACT FROM PUBLISHER]

A concurrent 10.5/25 GHz power amplifier (PA) is designed and implemented in a 0.18 μm CMOS technology. This PA employs dual‐band matching networks that can suppress harmonics, inter‐modulation products, and out‐of‐band signals so as to improve linearity performances. Moreover, the driver stage of the PA utilises a current‐reused topology which increases the gain without increase of the power dissipation. The chip size of the PA is 0.95 × 0.91 mm2 including testing pads, and its power consumption is 150 mW. The PA exhibits a measured gain of 15.2 and 6.8 dB, output P1dB of 10.5 and 9 dBm, Pout,max of 11.4 and 10 dBm and power added efficiency of 9 and 4.8% at 10.5 (f1) and 25 GHz (f2), respectively. The measured rejection of signals at 4 GHz (f2–2f1), 14.5 GHz (f2 − f1) and 21 GHz (2f1) is 43, 16.5 and 10.8 dB, respectively. [ABSTRACT FROM AUTHOR]