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In this work, a digital phase‐locked loop (DPLL) is proposed for the low power and stable operation in an augmented reality (AR) display system. The AR display system which needs the ultra‐low power consumption adopts the near‐threshold voltage (NTV) operation in both digital and analogue blocks. The NTV region has the advantage of small power dissipation with low‐supply voltage. However, it suffers from performance degradation due to a large delay, slow transition time, and small dynamic voltage range. To achieve the optimised power efficiency and stable performance, the dynamic time‐to‐digital converter and the low voltage optimised digitally controlled oscillator are applied in the proposed DPLL. In addition, the forward body biasing scheme is used to increase the operation frequency for the sigma‐delta modulator block. The proposed DPLL is fabricated using 65 nm CMOS technology and shows a current consumption of 160 μA at a voltage of 0.55 V. In addition, the jitter characteristic shows 6.7 ps rms jitter and 50 ps peak to peak jitter at 480 MHz. [ABSTRACT FROM AUTHOR]

In this paper, a second-order bang–bang digital phase-locked loop (BBPLL) with dominant random walk phase noise and transport delay is analyzed using Fokker–Plank equations. Explicit closed-form expressions are derived for the timing error probability distribution function, jitter variance, and power spectral density (psd). For the type-II BBPLL considered in this paper, the timing error distribution is shown to be Laplacian and not Gaussian distributed as previously assumed, while the derived psd is Lorentzian, which is consistent with earlier works. The analytical solutions are valid as long as the continuous-time approximation of the BBPLL dynamics is accurate as is the case for typical operating loop bandwidths. The accuracy of the derived expressions is validated via simulation. [ABSTRACT FROM AUTHOR]

A W-band integer-N all-digital phase-locked loop (ADPLL) aiming for wide frequency tuning range (TR) and low phase noise is proposed. The W-band ADPLL employs a digitally controlled oscillator (DCO) with split transformer and dual-path exponentially scaled switched-capacitor ladder and a clock-skew-sampling delta–sigma time-to-digital converter (TDC). The 65-nm CMOS W-band ADPLL measures a frequency TR of 27% from 82 to 107.6 GHz and phase noise from −106 to −110 dBc/Hz at 10-MHz offset and −84 to −87 dBc/Hz at 100-kHz offset while consuming 35.5 mW and occupying a 0.36 mm2 core area, corresponding to a figure of merit (FOM) of −171 ~ −173 dB and FOMT of −178 ~ −181 dB. [ABSTRACT FROM AUTHOR]

Abstract The carrier recovery loops are important in carrier tracking approaches particularly in the presence of high dynamic stress on user receivers and noisy environment applications. The precise carrier tracking techniques are proposed in systems that are sensitive to carrier mismatches, such as terrestrial or satellite tracking systems. The fading phenomenon, phase and frequency step changes and high user dynamics are currently most important challenges in the development of robust carrier tracking systems. In this work, a novel Digital Phase Locked Loop (DPLL) is proposed using type-2 fuzzy logic controller to improve noise immunity and handling user dynamic in digital receivers with application customization capability. Due to fast and accurate decision-making by proposed fuzzy logic controller, optimal loop filter coefficients are generated for DPLL. The proposed DPLL is simulated with Xilinx System Generator Software and can be implemented on FPGA. In comparison to traditional approaches, proposed new DPLL shows better performance in response to phase step, frequency step and frequency ramp signals with acceptable settling time alongside minimum complexity in implementation and customization. [ABSTRACT FROM AUTHOR]

A highly integrated three-state diplexer (TSD) on a single planar elliptical structure is for the first time presented in this paper. Three resonant modes are investigated in a planar elliptical resonator, e.g., two TM11 degenerate modes and one TM21 mode. These three resonant modes are designed to form three filtering channels, which are further combined to generate three states of a diplexer, namely, TSD. The planar elliptical triple-mode resonator is fed by three microstrip lines to form a triple-mode TSD. In order to validate the concept, the designed planar TSD is fabricated and measured. The measured results are in good agreement with the simulated ones. [ABSTRACT FROM AUTHOR]

In this paper, we present a low-power low-noise integer-N divider-less digital phase-locked loop (PLL) with high resolution. Phase detection is performed by a proposed analog-to-digital converter (ADC)-based time-to-digital converter composed of subsampling, charge pump (CP), time-domain variable-gain amplifier, and successive-approximation register (SAR) ADCs. Subsampling is well known for its high detection gain. The CP and the pulse generating circuit are also introduced to form the time-domain integral variable-gain amplifier, enhancing the resolution. An SAR ADC voltage signals into the digital domain, avoiding the use of analog filter which occupies large area. Moreover, compared to the conventional analog phase detectors, the SAR-ADC phase detector saves more area and power consumption. The novel PLL is implemented in a standard 65-nm CMOS process, occupying an area of 0.12 mm2. It presents an in-band phase noise of −108 dBc/Hz and an rms jitter of 357 fs at the operating frequency of 5 GHz. In addition, the proposed ADC-PLL achieves a competitively good figure of merit of 243 dB with a power consumption of only 3.9 mW. [ABSTRACT FROM AUTHOR]

Although often analyzed as a second-order system, digital phase-locked loop (DPLL) is actually a third-order system because of the intrinsic latency in the loop filter. The extra pole introduced by this additional clock latency requires the loop filter bandwidth to be correspondingly reduced to ensure stability. In many applications, however, the loop bandwidth needs to be as wideband as possible, since the digital-controlled oscillator (DCO) is often the dominant source of noise. A modified proportional–integral (PI) loop filter is proposed to widen the loop bandwidth. The proposed loop filter employs an additional internal feedback loop that causes a third-order DPLL system to effectively behave as a second-order system. The proposed loop filter is derived based on the observer-controller DPLL. An intuitive explanation based on pole-zero analysis suggests that a wider loop bandwidth can be employed than in the conventional PI loop filter, because the proposed loop filter pushes the extra pole to a higher frequency than in the conventional loop filter. Similarly, for the same open-loop unity gain frequency and phase margin, the proposed loop filter can place the zero at a higher frequency, enabling greater attenuation of the DCO noise while achieving the same lowpass filtering of the reference clock noise as in the conventional loop filter. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Madenat Al-Elem University College / Magallaẗ Kulliyyaẗ Madīnaẗ Al-ʿAlam Al-Ğāmi'aẗ is the property of Republic of Iraq Ministry of Higher Education & Scientific Research (MOHESR) and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

A novel electronically steerable phased array antenna is developed for global positioning system/broadband global area network (GPS/BGAN) navigation applications. The array is composed of 2 x 2 printed quadrifilar helical antennas (PQHAs) integrated with digital phase shifters for beam steering over the transmit/receive bands. The feed network of each PQHA is based on a sequential rotation to achieve wideband circular polarisation (CP). An elegant control network with the embedded microcontroller is designed to provide driving bits to the phase shifters with reduced phase error. The meandered line design maintains high-performance CP radiation up to ±60° off-axis, within 1525 to 1660 MHz, and its size is 44% of the design with straight lines. The array gain is positive over 1450-1800 MHz beyond the BGAN band, with better than 13 dB return loss and <2.2 dB axial ratio. The measured broadside gain of the array exceeds 8.5 dBi at 1600 MHz, and has a wide beam steering of ~ ±80° over the BGAN band. The developed antenna represents a significant technical advance to the design and manufacturing of PQHA array, it has a compact size, low cost and lightweight with a relatively large bandwidth and almost hemispherical coverage with excellent right-hand circularly polarized radiation. [ABSTRACT FROM AUTHOR]

A multirate fractional-N RF digital phase-locked loop (DPLL) phase modulator implementation for polar transmitter supporting cellular communication standards up to 4G LTE-A is demonstrated. The RF-DPLL integrates LC-tank-based digital-controlled oscillator (DCO) cores with $\Sigma $ – $\Delta $ -noise shaping and fractional sample rate conversion to account for a broad range of frequency bands and spectral emission requirements. A two-point modulation with different sampling rates and signal scaling is applied to optimize the system for operation in narrow-band and wide-band phase modulation. DCO digital predistortion and DCO gain estimation in combination with open-loop gain auto adjustment and delay calibration are implemented to achieve sufficiently low-in-band distortion. Measurement results of the RF-DPLL system as part of a polar transmitter implemented in 28-nm CMOS are shown, fulfilling 3GPP specifications for 4G, LTE-A uplink and legacy cellular communication standards like 3G, UMTS/HSPA+ and 2G, GSM/EDGE. [ABSTRACT FROM AUTHOR]

An all-digital reconfigurable multi-output clock generator is presented. A digital phase-locked loop provides a high-frequency clock to multiple independent open loop $\Delta \Sigma $ fractional dividers (FDIVs). A high resolution digital-to-time converter (DTC) whose range is calibrated in background is used to achieve low-jitter performance that is insensitive to process, voltage, and temperature variations. The proposed open loop FDIV operates over a wide frequency range of 20 MHz–1 GHz, and has programmable spread spectrum modulation and instantaneous frequency switching capabilities. Fabricated in a 65-nm process, the prototype FDIV occupies an active area of 0.017 mm2. At 1-GHz output frequency, it consumes 3.2 mW from 0.9-V supply and achieves a worst case integrated jitter of 1.44 psrms. [ABSTRACT FROM AUTHOR]

A pattern synthesis technique for real and coupled antenna arrays by using digital phase-only excitation weights is introduced here. The method is formulated as an integer linear programming problem incorporating a fast full-wave analysis of the array, based on the finite element method and spherical mode expansions. The method achieves radiation patterns with specified pointing directions, main lobe widths, minimum sidelobe level, and prescribed nulls, controlled by digital phase shifters. [ABSTRACT FROM AUTHOR]

For timing and synchronization system, digital phase-locked loop (DPLL) and Kalman filter all have been widely used as the clock tracking and clock correction schemes for the similar structure and properties. This paper compares the two schemes used for ultrawideband (UWB) location system. The improved Kalman filter is more immune to interference. [ABSTRACT FROM AUTHOR]

This article analyses the performance of the first-order zero crossing digital phase locked loops (FR-ZCDPLL) when fractional loop delay is added to loop. The non-linear dynamics of the loop is presented, analysed and examined through bifurcation behaviour. Numerical simulation of the loop is conducted to proof the mathematical analysis of the loop operation. The results of the loop simulation show that the proposed FR-ZCDPLL has enhanced the performance compared to the conventional zero crossing DPLL in terms of wider lock range, captured range and stable operation region. In addition, extensive experimental simulation was conducted to find the optimum loop parameters for different loop environmental conditions. The addition of the fractional loop delay network in the conventional loop also reduces the phase jitter and its variance especially when the signal-to-noise ratio is low. [ABSTRACT FROM PUBLISHER]

Digital phase-locked loop (DPLL) frequency synthesizers have become popular for wireless applications in the sub-10-GHz range. However, mm-wave synthesizers still rely on analog PLLs, predominantly of the sub-harmonic, integer-N-type. This paper describes the design and implementation of a 50–66-GHz phase-domain DPLL that uses a fundamental frequency capacitively degenerated digitally controlled oscillator (DCO) with 40-kHz frequency step. Following frequency division with a modulus of only 4, a two-step 8-bit time-to-digital converter (TDC) digitizes the phase of the 12.5–16.5-GHz divider output with 450-fs resolution. Digital calibration based on the statistical element selection technique augmented by mean adaptation is used to mitigate TDC nonlinearity that results from random mismatches. Additional digital calibration techniques are introduced to mitigate DCO non-linearity and phase mismatches in the digital phase extraction sub-system, and to ensure robust operation of the inductor-less 4 $\times $ frequency divider over process, voltage and temperature (PVT) variations. A 65-nm CMOS prototype of the DPLL occupies 0.45 mm2 excluding pads and consumes 46 mA from a 1-V supply. The PLL achieves best (worst) case rms jitter of 220 (302) fs, best (worst) phase noise of −83/−94.5/−122 (−79/−88/ −116) dBc/Hz at 0.1/1/10 MHz offset, and −52.2(−48.3) dBc fractional spur. [ABSTRACT FROM AUTHOR]

This paper presents a novel Time-to-digital converter (TDC) for All Digital Phase Locked Loop (ADPLL) able to reach high linearity and wide input range with normalized fractional output code. The topology is based on startable Pseudo differential delay cells. It arbiters in a gated ring oscillator (GRO) format in manner to extend measurement time interval. A normalization unit is developed to free calibrate output and to measure phase errors for divider-less ADPLL applications. The proposed TDC is designed in 90 nm CMOS process. Simulation results show that the TDC achieves a large detectable conversion range that extends between 0.285 and 10 ns. The attained time resolution is 9.4 ps, which corresponds to half the delay time of an inverter. The TDC is self-calibrating with estimated accuracy better than 0.28%. The structure consumes 6.6 mA current from a 1.0 V voltage supply, when operating at a clock frequency of 13 MSPS. The estimated differential nonlinearity and integral nonlinearity are ±0.48 LSB and ±0.6 LSB respectively. Compared to previously reported TDC, this implementation achieves a competitive FoM without requiring complicate calibration. [ABSTRACT FROM AUTHOR]

This paper presents a digital phase-locked-loop (DPLL) based on multi-output bang-bang phase detector (MOBBPD) with reused most significant bits (MSBs) of MOBBPD. The MOBBPD can be implemented simply while achieving the merits of both time-to-digital converter (TDC) and bang-bang phase detector (BBPD). The digital PLL's locking time can be reduced due to the multi-output comparing with the classical digital PLL's with standard BBPD. In order to further shorten the loop locking time, we propose to reuse the MSBs, which are trigged at the early stage of locking acquisition, such that the phase difference can quickly decrease. Because of its simple structure, the proposed DPLL can be designed without much effort. The prototype DPLL is fabricated in a standard 0.18-μm CMOS process. The measurement results show that the output clock frequency ranges from 0.768 to 1.344 GHz. The total measured power consumption is 4.7 mW and the measured locking speed is around 40 times faster than a typical design without reusing the MSBs at 1.024 GHz. [ABSTRACT FROM AUTHOR]

Quasi-optimal synthesis of digital phase-locking systems (PLSs) is discussed to evaluate the information parameters of a frequency-modulated signal. An adaptive Kalman filter capable of functioning without a priori data on the statistical characteristics of input and test noises is employed. The model of the process under study is identified using the linear trend modified by the self-organization algorithm. Procedures and the results of numerical calculations are presented for the digital system of phase synchronization. [ABSTRACT FROM AUTHOR]

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation. [ABSTRACT FROM AUTHOR]

Presents the table of contents for this issue of the publication. [ABSTRACT FROM AUTHOR]

Self-organized synchronization occurs in a variety of natural and technical systems but has so far only attracted limited attention as an engineering principle. In distributed electronic systems, such as antenna arrays and multi-core processors, a common time reference is key to coordinate signal transmission and processing. Here we show how the self-organized synchronization of mutually coupled digital phase-locked loops (DPLLs) can provide robust clocking in large-scale systems. We develop a nonlinear phase description of individual and coupled DPLLs that takes into account filter impulse responses and delayed signal transmission. Our phase model permits analytical expressions for the collective frequencies of synchronized states, the analysis of stability properties and the time scale of synchronization. In particular, we find that signal filtering introduces stability transitions that are not found in systems without filtering. To test our theoretical predictions, we designed and carried out experiments using networks of off-the-shelf DPLL integrated circuitry. We show that the phase model can quantitatively predict the existence, frequency, and stability of synchronized states. Our results demonstrate that mutually delay-coupled DPLLs can provide robust and self-organized synchronous clocking in electronic systems. [ABSTRACT FROM AUTHOR]

ABSTRACT An all-digital-phase-locked-loop (ADPLL) with a dual-mode Class-A/Class-C Digital-controlled-oscillator (DCO) is presented in this letter. During the start-up phase, the DCO operates in the Class-A mode with increasing tail current. A low-power amplitude-to-pulse-converter (APC) is proposed to detect the oscillating amplitude of the DCO. After the start-up, the DCO switches to the Class-C mode with reduced tail current, resulting in better phase noise and lower power consumption. The ADPLL with the proposed DCO is implemented in a 65-nm CMOS technology. The Class-C mode DCO exhibits a phase noise of −123.3 dBc/Hz at 1-MHz offset with a 2.7-GHz carrier frequency. Measured results show about a 2.9-dB phase noise improvement at 1-MHz offset among the tuning range of 2.5-2.9 GHz, compared to the Class-A DCO under the same power consumption. The figure-of-merit (FOM) and FOM including the tuning range (FOMT) of the DCO is 188.7 and 192.1, respectively. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:312-315, 2017 [ABSTRACT FROM AUTHOR]

This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (ASZCDPLL) to linearize the phase difference detection, and enhance the loop performance. The new loop has faster acquisition, less steady state phase error, and wider locking range as compared to the conventional ZCDPLL. The locking range improvement and faster acquisition have been confirmed through simulation. The loop has been implemented and tested in real time using Texas Instruments TMS320C6416 DSP development kit.

This brief presents a built-in self-calibration (BISC) technique for minimization of the total jitter in bang-bang all-digital phase-locked loops (ADPLLs). It is based on the addition of a monitoring phase-frequency detector (PFD) with tunable delay cells for the reference clock and the divider clock and a counter for this PFD output signal. This allows for on-chip binary comparison of the jitter distribution widths at the ADPLL PFD input, when ADPLL filter parameters are altered. Since only a relative comparison is performed, no accurate delay calibration is required. The statistical properties of this comparison of two random distributions are analyzed theoretically, and guidelines for circuit dimensioning are derived. The proposed method is used for BISC by adaption of the ADPLL filter coefficients. This allows for jitter minimization under process, voltage and temperature variations as well as gain and period jitter of the digitally controlled oscillator. The proposed calibration technique is verified by system simulations and measurements of a silicon prototype implementation in 28-nm CMOS technology. [ABSTRACT FROM PUBLISHER]

This paper proposes a fractional-N digital phase-locked loop (DPLL) architecture with feedforward multi-tone spur cancellation scheme. The proposed cancellation loop is capable of suppressing both internal spur, i.e., fractional-N spur, and externally coupled spur from input paths. It can be further extended for multi-stage operation for mitigating multiple spur sources. Both theoretical analysis and simulation results are provided in this paper to explore the design tradeoffs of the proposed technique. A proof-of-concept prototype is implemented in 65 nm CMOS. It measures external spur reduction of 15 to 35 dB and the worst-case fractional spur of 73.66 to 117 dBc with 20–50 dB improvement after enabling the cancellation loop. The measured reference spur ranges from 110.1 to 116.1 dBc across the entire DPLL operation range (3.2–4.8 GHz) thanks to design techniques. The measured in-band phase noise achieves 103 dBc at 100 kHz frequency offset and out-of-band phase noise of 122 dBc at 3 MHz frequency offset with integrated phase noise of 38.1 dBc from 10 kHz to 40 MHz. [ABSTRACT FROM AUTHOR]

This letter proposes a new moving-average form of digital phase-locked loop (DPLL) that uses the average value of measurements on a memory horizon and the correction term to estimate phase information. This ensures the desired unbiasedness property for the phase information. A new formula for the optimal memory size of the proposed DPLL with minimization of the expected squared phase error is established. A numerical example is given to show that the developed DPLL has superior robustness against quantization and incorrect noise compared to the existing DPLLs. [ABSTRACT FROM PUBLISHER]

All-digital phase-locked loops (ADPLLs) based on the time-to-digital converter (TDC) and the frequency discriminator (FD) are modeled and analyzed in terms of quantization effects. Using linear models with quantization noise sources, theoretical analysis and simulation are carried out to obtain the output phase noise of each building block of the TDC-based ADPLL. It is newly derived that the TDC noise component caused by the delta-sigma modulator (DSM) and the finite resolution of the digitally controlled oscillator is not white. Namely, the in-band phase noise caused by the DSM-induced TDC is not white, which is due to the integrate-and-dump and subsampling operations of the TDC. This can give some insight into the design of low-noise ADPLLs. Some structures of delta-sigma FDs, which can serve as an alternative to the TDC, are also newly analyzed in terms of quantization noise, using the derived linear noise model. [ABSTRACT FROM AUTHOR]

The upgraded millimeter-wave interferometer with the frequency of 70 GHz is installed on a largescaled negative ion source. Measurable line-averaged electron density is from 2 × 1015 to 3 × 1018m-3 in front of the plasma grid. Several improvements such as the change to shorter wavelength probing with low noise, the installation of special ordered horn antenna, the signal modulation for a high accuracy digital phase detection, the insertion of insulator, and so on, are carried out for the measurement during the beam extraction by applying high voltage. The line-averaged electron density is successfully measured and it is found that it increases linearly with the arc power and drops suddenly at the beam extraction. [ABSTRACT FROM AUTHOR]

A wide band fractional-N digital PLL which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) with 5.2 ps resolution is presented. The quantization noise shaping of the TDC greatly improves the in-band phase noise. While, in the same time, the 2-dimension structure makes the digital PLL (DPLL) be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO) and digital ΣΔ quantization noise cancellation based least mean square (LMS) algorithm, the DPLL achieves -110dBc/Hz and -140dBc/Hz for in-band and 10 MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz and 1 MHz bandwidth. The digital PLL is simulated in a 65 nm CMOS process, consuming 11.2 mW from a 1.0 V supply. [ABSTRACT FROM AUTHOR]

In this letter, we present a rotation-aided arctangent phase discriminator (RaAPD) with one-bit analog-to-digital conversion. Different from the existing digital phase discriminator (DPD) and noise-balanced digital phase discriminator (NB-DPD), the proposed RaAPD can achieve higher accuracy and better noise robust features through utilizing an extra rotation channel in the arctangent phase discriminator (APD). Experimental results show that RaAPD achieves 98.3%, 79.3%, and 79.4% reduction in terms of the average root-mean-square error of phase estimation with the signal noise ratio range [−20 dB, 20 dB] and a 16.384-MHz sampling frequency comparing to DPD, NB-DPD, and APD, respectively. [ABSTRACT FROM PUBLISHER]

Angle tracking loop in airborne radar systems is vital in 3D joint tracking loops of range, velocity, and angle. This study concerns two angle tracking issues when an airborne digital array radar system tracks a maneuvering target: slow convergence, and a divergent issue of tracking errors at the final tracking phase. A new angle tracking loop called “constant coefficient angle tracking loop filter” (CCATLF) based on digital phase-locked loop (DPLL) is proposed. To improve tracking performance, a novel algorithm called “adaptive angle tracking loop filter” (AATLF) is also proposed based on CCATLF. In this algorithm, an adaptive equivalent loop noise bandwidth is derived to adjust with the angle by solving an optimization problem that involves angle measuring value and beam pointing. A theoretical error variance formula and stability analysis of the loop are also presented. Experiment results demonstrate that the proposed AATLF algorithm performs better, and is more effective and robust compared with other angle tracking algorithms. [ABSTRACT FROM AUTHOR]

A fractional-N digital phase-locked loop (DPLL) with ring oscillator based injection-locked frequency divider (ILFD) and parallel sampling phase samplers is presented. The ILFD utilizes dual path injection technique to achieve wide locking range (4.2–23 GHz) and low power consumption. A low-power parallel sampling phase sampler based time-to-digital converter (TDC), which achieves sub-gate-delay resolution by sampling the ILFD’s multi-phase outputs using parallel sampling technique, is proposed. The TDC resolution is determined by delay spacing between successive sampling clocks, which is ensured through digital calibration loops. Due to injection locking, no calibration is required to normalize the TDC step to the DCO output period. A hybrid high speed counter architecture, combining a 2 bit asynchronous counter and a 6 bit synchronous counter, is proposed to achieve high speed (>4 GHz) operation with low power consumption. The proposed design is fabricated in a 65 nm CMOS process and occupies 0.1 mm2. The synthesizer covers 13.6–16.8 GHz output and dissipates 8.5 mW. The measured output phase noise achieves −89 dBc/Hz and −125 dBc/Hz at 100 kHz and 10 MHz offsets, respectively. The measured jitter is less than 0.43 ps. [ABSTRACT FROM PUBLISHER]

This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of - 112\; \textdBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of -242 \; \textdB was achieved with a power consumption of only 4.2 mW. [ABSTRACT FROM PUBLISHER]

The objective of this work is to analyse the performance of the newly proposed two-tap FIR digital filter-based first-order zero-crossing digital phase-locked loop (ZCDPLL) in the absence or presence of additive white Gaussian noise (AWGN). The introduction of the two-tap FIR digital filter widens the lock range of a ZCDPLL and improves the loop’s operation in the presence of AWGN. The FIR digital filter tap coefficients affect the loop convergence behaviour and appropriate selection of those gains should be taken into consideration. The new proposed loop has wider locking range and faster acquisition time and reduces the phase error variations in the presence of noise. [ABSTRACT FROM AUTHOR]

A direct sampling full-band capture (FBC) receiver for cable and digital TV applications is presented. It consists of a 0.18 μm BiCMOS low-noise amplifier (LNA) and a 28 nm CMOS direct RF sampling receiver based on a 2.7 GS/s analog-to-digital converter (ADC) embedded in a system-on-chip (SoC). Digital signal processing (DSP) plays critical roles to assist analog circuits in providing functionalities and enhancing performances, including digital automatic gain control (AGC), digital phase-locked loop (PLL), and digital ADC compensation. The receiver is capable of receiving 158 256 QAM channels from 48 to 1000 MHz simultaneously, achieving up to 10 Gb/s data throughput for data and video while exceeding Data over cable service interface specification (DOCSIS) and Society of Cable Telecommunications Engineers (SCTE) requirements. The CMOS receiver occupies 1 \text mm^2 area while consuming 300 mW. The LNA consumes 130 mW and occupies 3 \text mm^2 area. The total power dissipation from the receiver is 2.7 mW per 6 MHz channel when capturing the entire cable spectrum. [ABSTRACT FROM PUBLISHER]

In energy-efficient processing platforms, such as wearable sensors and implantable medical devices, dynamic voltage and frequency scaling allows optimizing the energy efficiency under various modes of operation. The clock generator used in these platforms should be capable of achieving a faster settling time and has a wider operating voltage range. In this brief, a fast lock-in all-digital phase-locked loop (ADPLL) with two operation modes (0.52/1 V) is presented. The proposed ADPLL can quickly compute the desired digitally controlled oscillator control code with high accuracy. Therefore, the proposed ADPLL can achieve a fast setting time with frequency errors <5% within four clock cycles. The proposed ADPLL is implemented using a standard performance 90-nm CMOS process. The output frequency of the ADPLL ranges from 60 to 600 MHz at 1 V, and from 30 to 120 MHz at 0.52 V. The power consumption of the proposed ADPLL is 0.92 mW at (1 V, 600 MHz), and 37 \mu \textW at (0.52 V, 120 MHz). [ABSTRACT FROM PUBLISHER]

This paper presents a wide-voltage-range, fast-transient all-digital buck converter using a high-resolution digital pulsewidth modulator (DPWM). The converter employs the multithreshold-voltage band-control technique to shorten its transient response. The DPWM uses an all-digital delay-locked loop (ADDLL) to control its cycle. The usage of ADDLL leads to the DPWM possessing a small area while maintaining high cycle resolution. Moreover, the proposed ADDLL-based cycle-controlled DPWM can achieve synchronization between its input and output. This decreases the loop delay of the proposed converter so that the system is easy to be stabilized. The prototype chips of both the ADDLL-based cycle-controlled DPWM and the all-digital buck converter are fabricated in 0.35- \mu \textm CMOS process. Measurement results of the cycle-controlled DPWM show that the duty cycle of its output is adjustable from 1% to 99% in a 0.78% increment per step when operating at 1 MHz. The measured transition time of the all-digital buck converter is <3.5\mu \texts when the load current changes from 50 to 500 mA, and vice versa. [ABSTRACT FROM PUBLISHER]

The input frequency limit of the conventional zero-crossing digital phase-locked loop (ZCDPLL) is due to the operating time of the digital circuitry inside the feedback loop. A solution that has been previously suggested is the introduction of a time delay in the feedback path of the loop to allow the digital circuits to complete their sample processing before the next sample is received. However, this added delay will limit the stable operation range and hence lock range of the loop. The objective of this work is to extend the lock range of ZCDPLL with time delay by using a chaos control. The tendency of the loop to diverge is measured and fed back as a form of linear stabilization. The lock range extension has been confirmed through the use of a bifurcation diagram, and Lyapunov exponent.

A compact low‐supply‐voltage yet low‐noise digital bang–bang PLL (DBBPLL) is proposed. The bang–bang phase detector is based on a dynamic double‐tail latch which enables high time‐to‐voltage gain and low input‐referred noise under tight power‐supply headroom. The ring‐based digitally controlled oscillator (DCO) is made of multiple gm‐controlled delay units and a constant‐gm‐biased current DAC. By combining these two blocks, the DCO can now better tolerate supply noise and process variations. A prototype DBBPLL has been implemented in a mainstream 28 nm CMOS process with a compact die area of 0.014 mm2. When operating at 2.6 GHz, it consumes 2.9 mW with 0.75 V supply and achieves low in‐band phase noise of −105 dBc/Hz. [ABSTRACT FROM AUTHOR]

A low-jitter, low-power LC-based injection-locked clock multiplier (ILCM) with a digital frequency-tracking loop (FTL) is presented. Based on a pulse gating technique, the proposed FTL continuously tunes the oscillator’s free-running frequency to ensure robust operation across PVT variations. The FTL resolves the race condition existing in injection-locked PLLs by decoupling frequency tuning from the injection path, such that the phase-locking condition is only determined by the injection path. This paper also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection-locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO’s lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of 0.25\;\textmm^2. The prototype ILCM generates output clock in the range of 6.75–8.25 GHz by multiplying the reference clock by 64. It achieves superior integrated jitter performance of 190\;\textfs\text{rms}, while consuming 2.25 mW power. This translates to an excellent figure-of-merit (FoM) of -251\;\textdB, which is the best reported high-frequency clock multiplier. [ABSTRACT FROM PUBLISHER]

Virtual absorbed energy of the piezoelectric patch actuator is a cost function for the optimal feedback gain which has been proved theoretically. Previously, simulations have shown that maximizing the virtual absorbed energy and minimizing the kinetic energy of the plate can obtain almost the same feedback gain. In this work, the performance of virtual absorbed energy is validated by experiments on the reduction of the vibration of a smart panel with decentralized control loops. Each control unit consists of a collocated piezoelectric patch actuator and accelerometer sensor with a single channel digital controller. The open loop sensor/actuator frequency response function with different physical parameters (such as dimensions of plate and actuator), has been analyzed numerically and experimentally, to enhance the stability of the control system. Since the system is not unconditionally stable, a digital phase lag compensator is designed to guarantee the stability for larger feedback gains. The stability of the multi-channel decentralized feedback control system has been assessed by the eigenvalue locus of the open loop transfer function matrix. The control effectiveness of the reduction of the panel kinetic energy has been assessed by error sensors. [ABSTRACT FROM AUTHOR]

A compact all-digital phase-locked loop (C-ADPLL) based on symmetrical binary frequency searching (BFS) with the same circuit is presented in this paper. The minimising relative frequency variation error Δη(MFE) rule is derived as guidance of design and is used to weigh the accuracy of the digitally controlled oscillator (DCO) clock frequency. The symmetrical BFS is used in the coarse-tuning process and the fine-tuning process of DCO clock frequency to achieve the minimum Δηof the locked DCO clock, which simplifies the circuit architecture and saves the die area. The C-ADPLL is implemented in a 0.13 μm one-poly-eight-metal (1P8M) CMOS process and the on-chip area is only 0.043 mm2, which is much smaller. The measurement results show that the peak-to-peak (Pk-Pk) jitter and the root-mean-square jitter of the DCO clock frequency are 270 ps at 72.3 MHz and 42 ps at 79.4 MHz, respectively, while the power consumption of the proposed ADPLL is only 2.7 mW (at 115.8 MHz) with a 1.2 V power supply. The measured Δηis not more than 1.14%. Compared with other ADPLLs, the proposed C-ADPLL has simpler architecture, smaller size and lower Pk-Pk jitter. [ABSTRACT FROM AUTHOR]

A scalable low-voltage signaling (SLVS) serial link transmitter for MIPI M-PHY is presented in this paper. It delivers 200-400 mV pp signals at date rates of 1.25-5.8 Gbps. The integrated circuit entity consists of the actual SLVS driver, an ADPLL-based clock synthesizer with a frequency multiplier, and an internal test signal generator with pseudo-random binary sequences. The circuit has been fabricated in a 40-nm CMOS process. The overall active die area is 0.2 mm, while the actual driver occupies only 190 μm. In this work it was confirmed that a low-power SLVS driver meets the stringent common-mode noise generation limits set for serial interfaces used in mobile devices. Noise power density remains below −138 dBm/Hz at all data rates. Total power consumption of the transmitter is kept low by utilizing dynamic CMOS pre-drivers and a low drop-out voltage regulator. It achieves power efficiency of 0.44-1.4 mW/Gbps with external clock and 2.6-4.7 mW/Gbps with clock synthesizer. [ABSTRACT FROM AUTHOR]

The article presents abstracts on electronics topics which include the design of a varactorless tunable oscillator, time-to-digital converter module in a digital phase locked loop circuit, and detection of an outout voltage of a voltage regulator.