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Integrated logic circuits using atomically thin, two‐dimensional (2D) materials offer several potential advantages compared to established silicon technologies such as increased transistor density, circuit complexity, and lower energy dissipation leading to scaling benefits. In this article, a novel approach to achieve tunable doping in 2D semiconductors is explored to achieve complementary transistors and logic integration. By selectively transferring WSe2 onto hBN and SiO2 substrates, complementary transistor behavior (n‐ and p‐type) was achieved using a UV light source and electrostatic activation. Furthermore, advanced characterization techniques, including high‐resolution transmission electron microscopy (HRTEM) and Kelvin probe force microscopy (KPFM), provided insights into the chemical composition and surface potential changes after UV writing. Finally, a logic inverter was successfully implemented using selectively photo‐induced doped WSe2 transistors, showcasing the potential for practical logic applications. This innovative method opens new avenues for designing energy‐efficient and reconfigurable 2D semiconductor circuits, addressing key challenges in modern electronics. [ABSTRACT FROM AUTHOR]

Power consumption plays a significant role in any integrated circuit. In this study, an explicit type pulse trigger flip-flop is implemented using the CMOS 90 nm technology. For low-power dissipation, 1 V supply will optimize the size of gate terminal. This explicit type flip-flop uses an explicit source for pulse generation, that is, the double edge-triggered pulse generator, which requires half of clock frequency compared to the single edge-triggered pulse generator. The proposed new double edge-triggered pulse generator uses the pulse generation logic, which is used to share many numbers of flip-flop results at low power. In this article, circuits with low power, low heat generation, and increased durability are achieved. [ABSTRACT FROM AUTHOR]

Tactile sensation is a highly desired function in robotics. Furthermore, tactile sensor arrays are crucial sensing elements in pulse diagnosis instruments. This paper presents the fabrication of an integrated piezoresistive normal force sensor through surface micromachining. The force sensor is transferred to a readout circuit chip via a temporary stiction effect handling process. The readout circuit chip comprises two complementary metal-oxide semiconductor operational amplifiers, which are redistributed to form an instrumentation amplifier. The sensor is released and temporarily bonded to the substrate before the transfer process due to the stiction effect to avoid the damage and movement of the diaphragm during subsequent flip-chip bonding. The released sensor is pulled off from the substrate and transferred to the readout circuit chip after being bonded to the readout circuit chip. The size of the transferred normal force sensor is 180 μm × 180 μm × 1.2 μm. The maximum misalignment of the flip-chip bonding process is approximately 1.5 μm, and sensitivity is 93.5 μV/μN/V. The routing of the piezoresistive Wheatstone bridge can be modified to develop shear force sensors; consequently, this technique can be used to develop tactile sensors that can sense both normal and shear forces. [ABSTRACT FROM AUTHOR]

Tactile sensation is a highly desired function in robotics. Furthermore, tactile sensor arrays are crucial sensing elements in pulse diagnosis instruments. This paper presents the fabrication of an integrated piezoresistive normal force sensor through surface micromachining. The force sensor is transferred to a readout circuit chip via a temporary stiction effect handling process. The readout circuit chip comprises two complementary metal-oxide semiconductor operational amplifiers, which are redistributed to form an instrumentation amplifier. The sensor is released and temporarily bonded to the substrate before the transfer process due to the stiction effect to avoid the damage and movement of the diaphragm during subsequent flip-chip bonding. The released sensor is pulled off from the substrate and transferred to the readout circuit chip after being bonded to the readout circuit chip. The size of the transferred normal force sensor is 180 μm × 180 μm × 1.2 μm. The maximum misalignment of the flip-chip bonding process is approximately 1.5 μm, and sensitivity is 93.5 μV/μN/V. The routing of the piezoresistive Wheatstone bridge can be modified to develop shear force sensors; consequently, this technique can be used to develop tactile sensors that can sense both normal and shear forces.

With the demand for high-performance and miniaturized semiconductor devices continuously rising, the development of innovative tunneling transistors via efficient stacking methods using two-dimensional (2D) building blocks has paramount importance in the electronic industry. Hence, 2D semiconductors with atomically thin geometries hold significant promise for advancements in electronics. In this study, we introduced tunneling memtransistors with a thin-film heterostructure composed of 2D semiconducting MoS 2 and WSe 2 . Devices with the dual function of tuning and memory operation were realized by the gate-regulated modulation of the barrier height at the heterojunction and manipulation of intrinsic defects within the exfoliated nanoflakes using solution processes. Further, our investigation revealed extensive edge defects and four distinct defect types, namely monoselenium vacancies, diselenium vacancies, tungsten vacancies, and tungsten adatoms, in the interior of electrochemically exfoliated WSe 2 nanoflakes. Additionally, we constructed complementary metal-oxide semiconductor-based logic-in-memory devices with a small static power in the range of picowatts using the developed tunneling memtransistors, demonstrating a promising approach for next-generation low-power nanoelectronics.

Based on negative feedback technique, a complementary metal–oxide semiconductor (CMOS) voltage reference with ultra‐low‐power, low supply voltage and high‐power supply rejection ratio (PSRR) is proposed and simulated using a 0.18 standard micrometre CMOS technology. The operating supply voltage ranges from 0.85 V to 2.5 V and the temperature ranges from −20°C to 80°C. The voltage reference can achieve a temperature coefficient of 16.3 ppm/°C and line sensitivity as low as 0.086 ppm/V, without the use of resistors or special devices, consuming 202 nA current at 27°C. Besides, the PSRR is only −113 dB at 1 Hz, −64 dB at 1 kHz, respectively.

Multiwall carbon nanotube (MWCNT) has been investigated as a potential interconnect material for future advanced technology nodes. The present paper analyzes performance of MWCNT interconnects using current mode signaling (CMS) scheme. The novelty of the present work can be stated as: Firstly, a unified model is proposed for both copper and MWCNT interconnects using finite-difference time-domain (FDTD) technique. Secondly, this model is applicable for both the conventional voltage mode signaling and more versatile CMS schemes. Furthermore, the presented FDTD-based model is valid for single as well as M-line coupled interconnects in integrated circuits. The model also incorporates CMOS gate as driver for MWCNT interconnect. Thirdly, power model using FDTD technique is investigated for the first time. Accurate formulation and computation of power dissipation in CMS MWCNT interconnects are presented in the paper. Propagation delay, power dissipation and power_delay_product (PDP) are the performance metrics considered for single-line CMS MWCNT interconnect. Crosstalk is analyzed for 2-Line and 5-Line coupled interconnects. It is investigated that CMS scheme leads to about 4 times lesser propagation delay and 2.5 times reduced PDP in MWCNT interconnect than the conventional copper interconnect for interconnect length of 4500 μm. The technology node considered is 32 nm. The response of the system is accurately computed using the proposed FDTD-based model. The maximum percentage error between results obtained by the proposed analytical model and SPICE simulation model is <3% for the various test cases. [ABSTRACT FROM AUTHOR]

Based on negative feedback technique, a complementary metal–oxide semiconductor (CMOS) voltage reference with ultra‐low‐power, low supply voltage and high‐power supply rejection ratio (PSRR) is proposed and simulated using a 0.18 standard micrometre CMOS technology. The operating supply voltage ranges from 0.85 V to 2.5 V and the temperature ranges from −20°C to 80°C. The voltage reference can achieve a temperature coefficient of 16.3 ppm/°C and line sensitivity as low as 0.086 ppm/V, without the use of resistors or special devices, consuming 202 nA current at 27°C. Besides, the PSRR is only −113 dB at 1 Hz, −64 dB at 1 kHz, respectively. [ABSTRACT FROM AUTHOR]

The exciting field of stretchable electronics (SE) promises numerous novel applications, particularly in-body and medical diagnostics devices. However, future advanced SE miniature devices will require high-density, extremely stretchable interconnects with micron-scale footprints, which calls for proven standardized (complementary metal-oxide semiconductor (CMOS)-type) process recipes using bulk integrated circuit (IC) microfabrication tools and fine-pitch photolithography patterning. Here, we address this combined challenge of microfabrication with extreme stretchability for high-density SE devices by introducing CMOS-enabled, free-standing, miniaturized interconnect structures that fully exploit their 3D kinematic freedom through an interplay of buckling, torsion, and bending to maximize stretchability. Integration with standard CMOS-type batch processing is assured by utilizing the Flex-to-Rigid (F2R) post-processing technology to make the back-end-of-line interconnect structures free-standing, thus enabling the routine microfabrication of highly-stretchable interconnects. The performance and reproducibility of these free-standing structures is promising: an elastic stretch beyond 2000% and ultimate (plastic) stretch beyond 3000%, with <0.3% resistance change, and >10 million cycles at 1000% stretch with <1% resistance change. This generic technology provides a new route to exciting highly-stretchable miniature devices. [ABSTRACT FROM AUTHOR]

An energy efficient high-speed adaptive finite impulse response filter with novel architecture is developed. Synthesis results along with novel architecture on different complementary metal–oxide semiconductor (CMOS) families are presented. Analysis is performed using Artix-7, Spartan-6 and Virtex-4 for most popular adaptive least mean square filter for different orders such as N = 8, 16, 32. The presented work is done using MATLAB (2013b) and Xilinx (14.2). From the synthesis results, it can be found that CMOS (28 nm) achieves the lowest power and critical path delay compared to others, and thus proves its efficiency in terms of energy. Different parameters are considered such as look up tables and input–output blocks, along with their optimised results.

In this paper, systematic analysis on the digital microphone is performed using energy dispersive X-ray spectroscopy (EDS) and transmission Kikuchi diffraction (TKD) in the scanning electron microscopy (SEM). Digital microphone is an integrated chip composed of complementary metal-oxide semiconductor (CMOS) and micro-electro-mechanical systems (MEMS). Using EDS, quantitative chemical composition and elemental maps on the integrated CMOS-MEMS-based microchip were obtained. Microanalytical X-Ray technique along with TKD was applied to reveal the nanostructure of the MEMS region, i.e., diaphragm membrane and then the CMOS region, i.e., tungsten through-silicon via. Device performance and lifetime were correlated with chemical diffusions, metal interface boundaries, grain structures, and phases existing at CMOS and MEMS junctions. Our results demonstrated that SEM-based TKD with EDS is a powerful microstructural characterization tool and performs vital role in failure analysis for device optimization. [ABSTRACT FROM PUBLISHER]

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxidesemiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications. [ABSTRACT FROM AUTHOR]

The architecture, design and implementation of a low power complementary metal‐oxide semiconductor (CMOS) class‐G audio amplifier with gradual power‐supply switching (GPSS) are presented. The proposed class‐G amplifier output stage strategically uses the parallel connection of a class‐AB output stage operating from smaller supplies (VDDL/VSSL), and a class‐C output stage (with crossover from VSSL to VDDL) operating from higher supplies (VDDH/VSSH). GPSS is achieved using an efficient biasing scheme with level shifters. Moreover, the proposed biasing scheme in conjunction with negative feedback enables low distortion during the power‐supply transition. Experimentally, the class‐G amplifier prototype achieves a −82.5 dB THD + N, a peak load power of 50 mW and a quiescent power consumption of 350 μW. The proposed class‐G amplifier was implemented in a standard CMOS 90 nm technology and occupies an active silicon area of 0.08 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a high-conversion gain, low-power, folded CMOS mixer for ZigBee application in 2.4 GHz of userbandwidth. The proposed mixer adapts current reuse technique to increase the conversion gain while substantiallyreducing the DC power dissipation. The current from LO stage is reused at the transconductance stage to reduce thepower consumption. This mixer is verified in 0.13 µm standard CMOS technology. The simulation result exhibits ahigh-conversion gain performance (CG) of 10 dB, 1 dB compression point (P1 dB) of -13.43 dBm, third-order interceptpoint (IIP3) of -4.3 dBm, and a noise figure of 16.67 dB. The circuit draws 675 µA current from the 1.2 V of supplyvoltage headroom. [ABSTRACT FROM AUTHOR]

This paper presents a novel technique for the integration of small complementary metal-oxide semiconductor (CMOS) chips into a large area substrate. A key component of the technique is the CMOS chip-based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 \mum larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for microelectromechanical systems micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI Semiconductor's 0.5 \mum CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 and 0.5 \mum, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. A CMOS/microfluidic hybrid system is also demonstrated based on the proposed integration technology. [ABSTRACT FROM PUBLISHER]

A low-power switchable dual-band complementary metal-oxide semiconductor (CMOS) low-noise amplifier (LNA) for 802.11a/b/g wireless local-area network applications is presented. The switched external capacitor is added to the gate-source node of the input transistor, which match to the input port in two frequency bands of 2.4 and 5.2 GHz. By just adding a small-size switched capacitor to the conventional source-degenerated topology, the proposed LNA has an advantage of occupying less chip area compared to other concurrent topology that uses more inductors by adopting LC tank resonators. In addition, it consumes less current compared to other topology which adopts a switched transistor technique. The proposed LNA is designed and simulated using a 0.18-μm CMOS technology. The LNA core draws only 2.3 mA from a 1 V supply voltage. The S11 and S22 of the proposed LNA are less than -10 dB in the two frequency bands. The noise figure is 3.2 and 3.5 dB at 2.4 and 5.2 GHz, respectively. The power gain is larger than 10 dB. The input IP3 is -2.9 and -3.1 dBm at 2.4 and 5.2 GHz, respectively. [ABSTRACT FROM AUTHOR]

This paper presents two voltage controlled oscillators (VCOs) operating at 5.42 and 5.76 GHz implemented in 0.18-\mum complementary metal-oxide semiconductor (CMOS) technology with integrated passive device (IPD) inductors. One IPD inductor was stacked on the top of the active region of the 5.76-GHz VCO chip, whereas the other IPD inductor was placed on the top of the 5.42-GHz VCO CMOS chip but far from the its active region. The high-quality IPD inductors reduce the phase noise of the VCOs. The measurements of the two VCOs indicate the same phase noise of -120∼dBc/Hz at 1 MHz offset frequency. These results demonstrate a 6-dB improvement compared to the VCO using an on-chip inductor. This paper also presents the effect of the coupling between the IPD inductor and the active region of the chip on the phase noise performance. [ABSTRACT FROM AUTHOR]

Wireless sensor network (WSN) applications are under extensive research and development due to the need to interconnect devices with each other. To reduce latency while keeping very low power consumption, the implementation of a wake-up receiver (WuR) is of particular interest. In WuR implementations, meeting high performance metrics is a design challenge, and the obtention of high-sensitivity, high data rate, low-power-consumption WuRs is not a straightforward procedure. The focus of our proposals is centered on power consumption and area reduction to provide high integrability and maintain a low cost-per-node, while we simultaneously improve circuit sensitivity. Firstly, we present a two-stage design based on a feedback technique and improve the area use, power consumption and sensitivity of the circuit by adding a current-reuse approach. The first solution is composed of a feedback amplifier, two op-amps plus a low-pass filter. The circuit achieves a sensitivity of –63.2 dBm with a power consumption of 6.77 µA and an area as low as 398 × 266 µm2. With the current-reuse feedback amplifier, the power consumption is halved in the second circuit (resulting in 3.63 µA), and the resulting circuit area is as low as 262 × 262 µm2. Thanks to the nature of the circuit, the sensitivity is improved to –75 dBm. This latter proposal is particularly suitable in applications where a fully integrated WuR is desired, providing a reasonable sensitivity with a low power consumption and a very low die footprint, therefore facilitating integration with other components of the WSN node. A thorough discussion of the most relevant state-of-the-art solutions is presented, too, and the two developed solutions are compared to the most relevant contributions available in the literature. [ABSTRACT FROM AUTHOR]

This paper reports a novel multidimensional complementary metal-oxide semiconductor (CMOS) based stress sensor. The device uses an octagonal n-well in a p-substrate and eight peripheral contacts enabling the current to be switched in eight directions rotated by an angle of π/4. By taking full advantage of the piezoresistive behavior of single-crystal silicon, the measurement of all in-plane stress tensor components, i.e., σxx, σyy, and σxy, is demonstrated. This information is derived from the zeroth and second angular-order Fourier components of voltage signals parallel and perpendicular to the switched current. Nonlinearities of the system are reduced by proper bias conditions using a center contact. The device was calibrated by applying defined normal stresses using a bending bridge setup. The device behavior was modeled including piezoresistive effects and the junction field effect by a combination of the finite element method and a nonlinear simulation program with integrated circuits emphasis (SPICE) network simulation using junction field effect transistor (JFET) elements. Stress sensitivities of 200 μV V-1 MPa-1 are demonstrated for the determination of the three stress components. [ABSTRACT FROM PUBLISHER]

N‐channel, lateral, double‐diffused MOS (NLDMOS) devices with finger‐type, square‐type, and octagon‐type layout styles are investigated and fabricated in a 0.5‐μm 18 V CMOS‐DMOS (CDMOS) process. The square‐type nLDMOS achieves the highest ESD failure current of 4.7 A and is also the device occupying the smallest chip area among the three layout styles. In view of the area efficiency, the square‐type structure provides more than 30 and 25% higher current handling capability per area than the traditional finger‐type and octagonal‐type structures, respectively. Because of its better area efficiency, the square‐type structure is a promising layout for nLDMOS in high‐voltage ESD protection applications. [ABSTRACT FROM AUTHOR]

A single‐stage multi‐path operational transconductance amplifier (OTA) is presented. The proposed amplifier uses the transconductance enhancing technique in an upgraded folded cascode (FC) amplifier. It significantly improves the DC gain, unity‐gain bandwidth and slew rate compared with previous FC amplifiers with the same power consumption. Simulation results in 90 nm complementary metal‐oxide semiconductor (CMOS) technology show that the proposed OTA achieves a 59.1 dB DC gain and a gain bandwidth of 650 MHz, which makes it suitable for fast‐settling switched‐capacitor circuits. [ABSTRACT FROM AUTHOR]

Abstract: MI-3 is a consortium of 11 universities and research laboratories whose mission is to develop complementary metal-oxide semiconductor (CMOS) active pixel sensors (APS) and to apply these sensors to a range of imaging challenges. A range of sensors has been developed: On-Pixel Intelligent CMOS (OPIC)—designed for in-pixel intelligence; FPN—designed to develop novel techniques for reducing fixed pattern noise; HDR—designed to develop novel techniques for increasing dynamic range; Vanilla/PEAPS—with digital and analogue modes and regions of interest, which has also been back-thinned; Large Area Sensor (LAS)—a novel, stitched LAS; and eLeNA—which develops a range of low noise pixels. Applications being developed include autoradiography, a gamma camera system, radiotherapy verification, tissue diffraction imaging, X-ray phase-contrast imaging, DNA sequencing and electron microscopy. [Copyright &y& Elsevier]

This letter describes the analysis and measurement of a complementary metal-oxide semiconductor (CMOS) quadrature-balanced current-mode mixer with a 90deg branch-line hybrid coupler and self-switching current-mode devices. The proposed mixer, using 0.13 mum 1P8M CMOS technology, can downconvert a 60 GHz RF signal to a 2 GHz intermediate frequency (IF) signal, with a local-oscillator power of 0 dBm at 58 GHz. In the design, the mixer had a single-end conversion gain of 1 dB and an input-referred 1 dB compression point of 2 dBm. The LO-RF isolation of the mixer can achieve -37 dB while using 3 mA from a supply voltage of 1.2 V. [ABSTRACT FROM PUBLISHER]

This letter presents a new quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two first-harmonic injection-locked oscillators (ILOs). The outputs of one ILO are injected to the gates of the tail transistors on the other ILO and vice versa so as to force the two ILOs operate in quadrature. The proposed CMOS QVCO has been implemented with the TSMC 0.18 mum CMOS technology and the die area is 0.582 times 0.972 mm2. At the supply voltage of 1.0 V, the total power consumption is 8.0 mW. The free-running frequency of the QVCO is tunable from 5.31 GHz to 5.75 GHz as the tuning voltage is varied from 0.0 V to 1.0 V. The measured phase noise at 1 MHz offset is -120.01 dBc/Hz at the oscillation frequency of 5.31 GHz and the figure of merit (FOM) of the proposed QVCO is about -185.48 dBc/Hz. [ABSTRACT FROM PUBLISHER]

Previous research has shown that the use of back-end-of-line (BEOL) light directing structures with silicon hot carrier light sources in a complementary metal-oxide semiconductor results in improved light extraction efficiency. This work focuses on the design of an improved back-end-of-line structure for improving light extraction efficiency when using substrate-based silicon light emitters. With the use of FRED optical engineering ray-tracing software, it was found that a significant amount of generated light is lost at the material interfaces of the optical structure, including losses due to significant internal reflections. Therefore, an optimized optical structure was designed to reduce internal reflections at the base of the structure. Simulation results show a 33.6% improvement in light extraction efficiency over the previously designed parabolic optical structure, over the visible spectrum. The light sources were tested using a parameter analyzer, radiometer, spectrometer, and goniometer. It was calculated that the luminance exiting the optimized optical structure had a 55.66-factor improvement over the control structure and a 1.35-factor improvement over the parabolic structure. Furthermore, the optimized structure had a 1.38-factor improvement in light extraction efficiency over the parabolic structure. Overall, the improved designed pipe-like BEOL light directing structure helped to improve the device luminescence and light emission direction from the light source, which invariably increased the light extraction efficiency. [ABSTRACT FROM AUTHOR]

Previous research has shown that the use of back-end-of-line (BEOL) light directing structures with silicon hot carrier light sources in a complementary metal-oxide semiconductor results in improved light extraction efficiency. This work focuses on the design of an improved back-end-of-line structure for improving light extraction efficiency when using substrate-based silicon light emitters. With the use of FRED optical engineering ray-tracing software, it was found that a significant amount of generated light is lost at the material interfaces of the optical structure, including losses due to significant internal reflections. Therefore, an optimized optical structure was designed to reduce internal reflections at the base of the structure. Simulation results show a 33.6% improvement in light extraction efficiency over the previously designed parabolic optical structure, over the visible spectrum. The light sources were tested using a parameter analyzer, radiometer, spectrometer, and goniometer. It was calculated that the luminance exiting the optimized optical structure had a 55.66-factor improvement over the control structure and a 1.35-factor improvement over the parabolic structure. Furthermore, the optimized structure had a 1.38-factor improvement in light extraction efficiency over the parabolic structure. Overall, the improved designed pipe-like BEOL light directing structure helped to improve the device luminescence and light emission direction from the light source, which invariably increased the light extraction efficiency. [ABSTRACT FROM AUTHOR]

We assessed interventional radiologists' task-based image quality preferences for two- and three-dimensional images obtained with a complementary metal-oxide semiconductor (CMOS) flat-panel detector versus a hydrogenated amorphous silicon (a-Si:H) flat-panel detector. CMOS and a-Si:H detectors were implemented on identical mobile C-arms to acquire radiographic, fluoroscopic, and cone-beam computed tomography (CBCT) images of cadavers undergoing simulated interventional procedures using low- and high-dose settings. Images from both systems were displayed side by side on calibrated, diagnostic-quality displays, and three interventional radiologists evaluated task performance relevant to each image and ranked their preferences based on visibility of pertinent anatomy and interventional devices. Overall, CMOS images were preferred in fluoroscopy ( p = 0.002 ) and CBCT ( p = 0.004 ), at low-dose settings ( p = 0.001 ), and for tasks associated with high levels of spatial resolution [e.g., fine anatomical details ( p = 0.006 ) and assessment of interventional devices ( p = 0.015 )]. No significant difference was found for fluoroscopic imaging tasks emphasizing temporal resolution ( p = 0.072 ), for radiography tasks ( p = 0.825 ), when using high-dose settings ( p = 0.360 ), or tasks involving general anatomy ( p = 0.174 ). The image quality preferences are consistent with reported technical advantages of CMOS regarding finer pixel size and reduced electronic noise., (© 2020 Society of Photo-Optical Instrumentation Engineers (SPIE).)

Along with ultralow-energy delay products and symmetric complementary polarities, carbon nanotube field-effect transistors (CNT FETs) are expected to be promising building blocks for energy-efficient computing technology. However, the work frequencies of the existing CNT-based complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are far below the requirement (850 MHz) in state-of-art wireless communication applications. In this work, we fabricated deep submicron CMOS FETs with considerably improved performance of n-type CNT FETs and hence significantly promoted the work frequency of CNT CMOS ICs to 1.98 GHz. Based on these high-speed and sensitive voltage-controlled oscillators, we then presented a wireless sensor interface circuit with working frequency up to 1.5 GHz spectrum. As a preliminary demonstration, an energy-efficient wireless temperature sensing interface system was realized combining a 150 mAh flexible Li-ion battery and a flexible antenna (center frequency of 915 MHz). In general, the CMOS-logic high-speed CNT ICs showed outstanding energy efficiency and thus may potentially advance the application of CNT-based electronics.

The influence of electrothermal behaviour on radio frequency (RF) performances of 28 nm bulk complementary metal–oxide semiconductor technology is examined. Biased continuous‐wave RF and pulsed RF (applying different DC pulse and RF pulse width combinations) characterisations are performed within the 1–30 GHz frequency domain at room temperature and the transit frequency (fT) is extracted at 15 GHz frequency. It has been found that the degradation in fT on I/O devices is about 3 GHz because of the self‐heating effect. [ABSTRACT FROM AUTHOR]

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Purpose: To evaluate the image quality generated by eight commercially available intraoral sensors., Methods: Eighteen clinicians ranked the quality of a bitewing acquired from one subject using eight different intraoral sensors. Analytical methods used to evaluate clinical image quality included the Visual Grading Characteristics method, which helps to quantify subjective opinions to make them suitable for analysis., Results: The Dexis sensor was ranked significantly better than Sirona and Carestream-Kodak sensors; and the image captured using the Carestream-Kodak sensor was ranked significantly worse than those captured using Dexis, Schick and Cyber Medical Imaging sensors. The Image Works sensor image was rated the lowest by all clinicians. Other comparisons resulted in non-significant results., Conclusions: None of the sensors was considered to generate images of significantly better quality than the other sensors tested. Further research should be directed towards determining the clinical significance of the differences in image quality reported in this study., (© 2016 FDI World Dental Federation.)

Impedance spectroscopy is a powerful tool for characterizing materials that exhibit a frequency dependent behaviour to an applied electric field. This paper introduces a fully integrated multi-channel impedance extraction circuit that can both generate AC stimulus signals over a broad frequency range and also measure and digitize the real and imaginary components of the impedance response. The circuit was fabricated in a 0.5μm complementary metal-oxide semiconductor. Tailored for cellular membrane interface characterization, the signal generator produces sinusoidal waves from 10mHz to 10kHz. To suit a variety of applications, the impedance extraction circuit provides a programmable current measurement range from 100pA to 100nA with a measured resolution of approximately 100fA. Occupying only 0.045mm² per measurement channel, the circuit is compact enough to include nearly 200 channels in a 3x3mm² die area. [ABSTRACT FROM AUTHOR]

Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries. [ABSTRACT FROM AUTHOR]

This chapter introduces to electronic cameras, discusses the various parameters considered for evaluating their performance, and describes some of the key features of different camera formats. The chapter also presents the basic understanding of functioning of the electronic cameras and how these properties can be exploited to optimize image quality under low-light conditions. Although there are many types of cameras available for microscopy, the most reliable type is the charge-coupled device (CCD) camera, which remains preferred for high-performance systems. If time resolution and frame rate are of no concern, slow-scan CCDs certainly offer the best available performance, both in terms of the signal-to-noise ratio and their spatial resolution. Slow-scan cameras are thus the first choice for experiments using fixed specimens such as measurements using immune fluorescence and fluorescence in situ hybridization. However, if video rate imaging is required, one need not evaluate slow-scan CCD cameras. A very basic video CCD may suffice if samples are heavily labeled or are not perturbed by high intensity illumination. When video rate imaging is required for very dim specimens, the electron multiplying CCD camera is probably the most appropriate at this technological stage. Intensified CCDs provide a unique tool for applications in which high-speed gating is required. The variable integration time video cameras are very attractive options if one needs to acquire images at video rate acquisition, as well as with longer integration times for less bright samples. This flexibility can facilitate many diverse applications with highly varied light levels., (Copyright © 2007 Elsevier Inc. All rights reserved.)