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Phase noise measurement of Phase Locked Loop (PLL) in automated test equipment (ATE) is expensive and time-consuming. Indirect phase noise measurement relies on a few correlated low-cost measurements called signatures obtained from specific nodes of the PLL. A regression model using these signatures is learned during the design phase for phase noise estimation. Extraction of these signatures and phase noise performance in PLL requires significant simulation time, raising non-recurring design costs and computer aided design (CAD) tool usage costs. In this work, a new methodology for indirect phase noise measurement is developed where Generative Adversarial Network (GAN), a deep learning framework, has been used for generating a substantial amount of model-driven synthetic signatures that are strongly correlated to simulation-driven real signatures. These model-driven signatures are then used to construct a regression model for phase noise prediction. The GAN model efficacy is verified by comparing the prediction accuracy of the simulation-driven signature-based model with the GAN-augmented signature-based regression model. [ABSTRACT FROM AUTHOR]

High-voltage and analog measurements occupy a large amount of automated test equipment (ATE) overhead. A method for realizing trimming automation through mixed digital and analog circuits is proposed. Taking a 40 nm 1 MB Flash chip test as an example, current high-voltage and analog quantity trimming accounts for 6.9% of the total test time. Through adding digital and analog circuits to the Built-In Self-Test (BIST) circuit, the trimming test time is reduced from 2.94 s to 0.23 s, and the ratio of the total test time is reduced to 0.58%. Compared with the original chip probing (CP) total time, the total time is reduced by 6.35%, the ATE overhead accounts for 19.35% of the total test time, and the Flash area is 0.63%. The measurement accuracy reaches 750 μV~6 mV, and the measurement error is 0.15% ± 7 mV, compared with the conventional ATE trimming method. [ABSTRACT FROM AUTHOR]

This paper utilizes the digital integrated circuit testing model to compute the test yield curve of future wafers and explore the influence of test guardband (TGB) on quality and yield. With the passage of three years since the COVID-19 pandemic disrupted semiconductor production lines, the semiconductor manufacturing industry still faces chip shortages. Although initiatives such as the CHIPS and Science Act in the United States have helped stabilize chip supply chains, manufacturers still face inventory shortages and delayed deliveries. Moreover, the backwardness and inaccuracy of semiconductor test equipment have led to a decline in both test yield and wafer quality, resulting in reduced shipments. Therefore, to mitigate yield losses and enhance the test yield and shipment volume of semiconductor products, this paper proposes a diverse test method (DTM) to improve test outcomes through the alteration of the testing strategy and TGB adjustment. Furthermore, according to the wafer estimation table published in the IEEE International Roadmap for Devices and Systems (2023), the proposed DTM can effectively enhance the test yield of wafers and improve the testing capabilities of ATE testers (automatic test equipment). Consequently, suppliers can stabilize the chip supply chain and enhance their companies' profits and reputation by improving chip test yield. [ABSTRACT FROM AUTHOR]

The circular scan architecture (CSA) is a widely used scan design technique in digital circuit testing that involves scanning test data through a circuit in a circular pattern. Several optimization approaches have been suggested so far to lessen the Test Data Volume (TDV), but no one has shown satisfactory results. Therefore, this paper proposes a Modified and Customized Wingsuit Flying Search algorithm to decrease the test data volume time. The proposed MCWFS-SBA-CSA introduces some novel features that distinguish it from traditional circular scan approaches. The concept of wingsuit flying is an innovative approach in the field of scan systems. This allows the scan that moves more dynamically and efficiently, enabling it to cover a larger area in a shorter time than traditional circular-scan approaches. After this phase, only scan-chosen inputs are required to obtain the next test pattern from the captured response. Therefore, required less Automatic test equipment (ATE) memory in this research so there is a Decreased cost in system-on-chip (SOC). The proposed method attains fast global searching capacity. The efficiency of the proposed technique attains 26.42%, 32.45%, and 29.34% higher compression ratio (CR), Test Application Time (TAT) reduction of SC-128 attains 29.45%, 34.67%, and 40.22% higher, TDV of SC-256 attains 32.23%, 36.34%, and 39.23% higher than existing methods, such as TDV for Circular Scan Approaches utilizing Modified Shuffled Shepard Optimization (TDV-CSA-MSSO), Effectual Very-large-scale integration Test data compression system for CSA under modified and colony metaheuristic (ETDC-CSA-MACMH), and Test Data Compression Utilizing Tetrad state Skip System (TDC-DC-TSSC) for Digital Circuits, respectively. [ABSTRACT FROM AUTHOR]

With the development of system-on-chip (SoC) and chiplet technology in the post-Moore era, an increasing number of chiplets are being integrated into a single chip. Consequently, the functions and complexity that can be realized are growing daily. Simultaneously, the volume of test data required for ultra-large-scale integrated circuits (ULSIs) has risen significantly. However, traditional automatic test equipment (ATE) is constrained by its data storage and bandwidth limitations, and its long technology iteration cycle. These cannot keep pace with the rapid development of design technology. This discrepancy leads to challenges in ULSI testing, such as excessively long test time and difficulties in completing the tests. Test compression technology can effectively address these issues by reducing the performance requirements of the test equipment, which in turn can lower test costs. This paper summarizes the classifications of chip test compression technology and, based on their current development, provides a detailed analysis of key technologies. It includes test compression-oriented coding methods, optimization of scan chain structures, and enhancements in coding for compression efficiency. Finally, a forward-looking perspective on the development of chip test compression technology is presented. The aim is to offer a reference for subsequent research in this field and related areas, as well as to provide technical support for the advancement of ULSI testing in the post-Moore era. [ABSTRACT FROM AUTHOR]

This paper introduces a novel approach to pavement material crack detection, classification, and segmentation using advanced deep learning techniques, including multi-scale feature aggregation and transformer-based attention mechanisms. The proposed methodology significantly enhances the model's ability to handle varying crack sizes, shapes, and complex pavement textures. Trained on a dataset of 10,000 images, the model achieved substantial performance improvements across all tasks after integrating transformer-based attention. Detection precision increased from 88.7% to 94.3%, and IoU improved from 78.8% to 93.2%. In classification, precision rose from 88.3% to 94.8%, and recall improved from 86.8% to 94.2%. For segmentation, the Dice Coefficient increased from 80.3% to 94.7%, and IoU for segmentation advanced from 74.2% to 92.3%. These results underscore the model's robustness and accuracy in identifying pavement cracks in challenging real-world scenarios. This framework not only advances automated pavement maintenance but also provides a foundation for future research focused on optimizing real-time processing and extending the model's applicability to more diverse pavement conditions. [ABSTRACT FROM AUTHOR]

The Milky Way's Central Molecular Zone (CMZ) differs dramatically from our local solar neighbourhood, both in the extreme interstellar medium conditions it exhibits (e.g. high gas, stellar, and feedback density) and in the strong dynamics at play (e.g. due to shear and gas influx along the bar). Consequently, it is likely that there are large-scale physical structures within the CMZ that cannot form elsewhere in the Milky Way. In this paper, we present new results from the Atacama Large Millimeter/submillimeter Array (ALMA) large programme ACES (ALMA CMZ Exploration Survey) and conduct a multi-wavelength and kinematic analysis to determine the origin of the M0.8–0.2 ring, a molecular cloud with a distinct ring-like morphology. We estimate the projected inner and outer radii of the M0.8–0.2 ring to be 79″ and 154″, respectively (3.1 pc and 6.1 pc at an assumed Galactic Centre distance of 8.2 kpc) and calculate a mean gas density >104 cm−3, a mass of ~106 M⊙, and an expansion speed of ~20 km s−1, resulting in a high estimated kinetic energy (>1051 erg) and momentum (>107 M⊙ km s−1). We discuss several possible causes for the existence and expansion of the structure, including stellar feedback and large-scale dynamics. We propose that the most likely cause of the M0.8–0.2 ring is a single high-energy hypernova explosion. To viably explain the observed morphology and kinematics, such an explosion would need to have taken place inside a dense, very massive molecular cloud, the remnants of which we now see as the M0.8–0.2 ring. In this case, the structure provides an extreme example of how supernovae can affect molecular clouds. [ABSTRACT FROM AUTHOR]

Modern embedded nanoelectronic devices, particularly in safety-critical sectors, require high dependability throughout their lifecycle. To address this, designers have started integrating extra circuitry for on-device self-testing, such as the Logic Built-In Self-Test (LBIST). However, while automatic test equipment (ATE) ensures exhaustive testing during manufacturing, in-field testing capabilities are limited. This study introduces a novel methodology for in-field data collection of failure information from LBIST engines and a subsequent logic diagnosis strategy to facilitate failure analysis of field returns. The information is collected from key-on and key-off self-tests, executed by central processing units (CPUs) with a fixed seed and different frequency configurations, primarily addressing transition delay (TRN) faults. The proposed approach capitalizes on the constrained in-field configurability of LBIST and does not require a custom architecture, making it highly practical and readily applicable to real-world devices. The logic diagnosis strategy significantly reduces the number of candidate faults by exploiting the first failing pattern index found during the in-field testing and data collection. Reducing fault candidates could enhance accuracy during failure analysis, especially when field return devices exhibit a "No Trouble Found" (NTF) behavior. The experimental results are reported for ITC'99 benchmarks and an industrial automotive system-on-chip (SoC) produced by STMicroelectronics, with about 20 million gates. [ABSTRACT FROM AUTHOR]

This paper discusses a comprehensive failure analysis approach to digital failures. High-resolution targeted patterns (HRTP) are highlighted along with their advantages in failure analysis by aiding in automated test pattern generation (ATPG) diagnoses resolution improvement, increasing the chance of detecting fault not detected by patterns implemented on automated test equipment (ATE), determine a potential test screen, provide stimulus for further fault localization, and increase the analysis success rate. This comprehensive approach and the use of HRTP have proven very helpful in the analysis of internal requests and customer returns. Three cases will be discussed in this paper to highlight these advantages. [ABSTRACT FROM AUTHOR]

A junior-level four-unit electronics curriculum is described in which students learn by building their own automated electronic test equipment and performing a rigorous suite of electronics experiments outside the classroom. Each student builds an electronics "workbench" based on an Arduino Nano microcontroller under the control of a software scripting environment (in our case, MATLAB). In the course of their work, students (1) construct a DC power supply and function generator and iteratively add programmable serial interfaces; (2) create an oscilloscope and spectrum analyzer that provides real-time displays of two analog channels for measurement of AC voltage amplitudes, frequency, and phase difference; (3) automate measurements of device I–V curves and transistor gain; (4) design, build, and characterize audio amplifiers and filters through measurement of time constants and frequency responses; and (5) compare the measured and simulated Bode plots. Mixing unconventional topics such as automation, numerical simulation, and programming with basic electronics removes the drudgery of data collection and provides more exposure, repetition, and organization of key concepts. Without being restricted to making measurements within the imposed lab schedule, students can work where and when they are able, repeat automated experiments in seconds, and continue exploring electronics with their workbench. After completing this course, our students demonstrate more confidence and capability with integrating electronics, automation, and programming into other projects and in improving existing systems. Likewise, students glean hands-on experience with scripting repetitive activities, saving enormous effort in their data-gathering work and leaving more time for analysis and creativity. Editor's Note: In this paper, the author describes a junior-level flipped electronics instructional laboratory that combines electronics and computer interfacing instruction in one course. Students are provided with a low-cost electronics kit (including an Arduino microcontroller, a handheld multimeter, and various circuit components), along with a MATLAB license, from which they build a versatile electronics workbench at home. Many of the labs involve building permanent apparatus, including a programmable DC power supply and function generator, a spectrum analyzer, and an oscilloscope, that the students use to measure I–V characteristic curves, characterize transistors, work with Fourier transforms, Bode plots, and so on. Using their workbench, each student can work on their lab projects outside of the classroom whenever and wherever it is convenient for them. Various supplementary materials, including code, are provided, which are useful for those wishing to implement this curriculum at their own institution. [ABSTRACT FROM AUTHOR]

High-precision and rapid detection of apparent defects in subway tunnel linings is crucial for ensuring the structural integrity of tunnels and the safety of train operations. However, current methods often do not adequately account for the spatial characteristics of these defects and perform poorly in detecting and extracting small-scale defects, which limits the accuracy of detection and geometric parameter extraction. To address these challenges, this paper proposes an efficient algorithm for detecting and extracting apparent defects in subway tunnels. Firstly, YOLOv8 was selected as the foundational architecture due to its comprehensive performance. The coordinate attention module and Bottleneck Transformer 3 were then integrated into the model's backbone to enhance the focus on defect-prone areas and improve the learning of feature relationships between defects and other infrastructure. Subsequently, a high-resolution detection layer was added to the model's head to further improve sensitivity to subtle defects. Additionally, a low-quality crack dataset was created using an open access dataset, and transfer learning combined with Real-ESRGAN was employed to enhance the detail and resolution of fine cracks. The results of the field experiments demonstrate that the proposed model significantly improves detection accuracy in high-incidence areas and for small-scale defects, achieving a mean average precision (mAP) of 87% in detecting cracks, leakage, exfoliation, and related infrastructure defects. Furthermore, the crack enhancement techniques substantially improve the representation of fine-crack details, increasing feature extraction accuracy by a factor of four. The findings of this paper could provide crucial technical support for the automated operation and maintenance of metro tunnels. [ABSTRACT FROM AUTHOR]

Reading comprehension is the ultimate goal of learning to read, as the understanding of text is at the root of the purpose for reading, whether reading for pleasure or reading to learn. At-home reading practices can vary widely family to family – some families have the knowledge and resources to read effectively with their children, while others have not been afforded the opportunity or knowledge to read with their children. The Advancing Comprehension and Engagement (ACE) Literacy Project is a free reading comprehension resource bringing the evidence-based Knowledge Acquisition & Transformation (KAT) Framework to families via podcast and video episodes in English and Spanish. The aim of the ACE Project is to help ameliorate access barriers to high-quality literacy resources for families by providing engaging, interactive episodes available on major platforms and accessible via cell phones, tablets, or computers. The present article describes the theoretical foundations underlying the ACE Project, details the methods used to develop ACE, describes the format followed in each episode, and discusses the pilot year of the project. Usage statistics are presented. Implications for the future of the ACE Project are discussed in light of initial data collection. [ABSTRACT FROM AUTHOR]

This innovative project aims to increase the effectiveness and user experience of solar panel systems by introducing a state-of-the-art dust and speck removal system. Leveraging cutting-edge technology, the system demonstrates a remarkable 32% increase in power output compared to dirty solar panels. The approach is characterized by its reliance on the universe as the system controller, reducing the need for manual intervention and minimizing the workforce required for panel cleaning. The proposed timed system utilizes water and wipers, facilitated by internet of things (IoT) technology, microcontrollers, and sensor modules for efficient and automated operation. An Android application provides user control and notifications about ongoing processes. The system's adaptability for various settings is emphasized, offering a portable solution. The smart IoT based automatic solar panel cleaning ensures reliable performance, underscoring the project's commitment to improve scalability, cost-efficiency, performance, integrity, and consistency. [ABSTRACT FROM AUTHOR]

Robotic inspection is advancing in performance capabilities and is now being considered for industrial applications beyond laboratory experiments. As industries increasingly rely on complex machinery, pipelines, and structures, the need for precise and reliable inspection methods becomes paramount to ensure operational integrity and mitigate risks. AI-assisted autonomous mobile robots offer the potential to automate inspection processes, reduce human error, and provide real-time insights into asset conditions. A primary concern is the necessity to validate the performance of these systems under real-world conditions. While laboratory tests and simulations can provide valuable insights, the true efficacy of AI algorithms and robotic platforms can only be determined through rigorous field testing and validation. This paper aligns with this need by evaluating the performance of one-stage models for object detection in tasks that support and enhance the perception capabilities of autonomous mobile robots. The evaluation addresses both the execution of assigned tasks and the robot's own navigation. Our benchmark of classification models for robotic inspection considers three real-world transportation and logistics use cases, as well as several generations of the well-known YOLO architecture. The performance results from field tests using real robotic devices equipped with such object detection capabilities are promising, and expose the enormous potential and actionability of autonomous robotic systems for fully automated inspection and maintenance in open-world settings. [ABSTRACT FROM AUTHOR]

The imperative need to advance the development of more efficient electric motors requires the meticulous measurement of small increments while minimizing the associated uncertainty in dynamometer tests. One of the key variables in such tests is the angular speed, which is typically obtained based on encoder measurements. This paper proposes a systematic measurement uncertainty assessment method based on the Guide to the Expression of Uncertainty for the two most widely used methods for angular speed measurement, namely, the frequency and period methods. In addition, the impact of the angular speed calculation method on the efficiency test uncertainty is assessed using an automatic test rig for electric motors. Our experimental results consider both steady-state and dynamic analyses. The results show that the period measurement method provides measurements with lower uncertainty for the encoders typically used in such test rigs, about 30 times less than the uncertainty determined for the frequency measurement method. Based on these results, the choice of a proper method can drastically decrease the angular speed uncertainty, and consequently the motor efficiency uncertainty, without increasing instrumentation cost. [ABSTRACT FROM AUTHOR]

The use of automated equipment for surface crack detection based on digital image acquisition is becoming increasingly popular in the inspection industry. While researchers typically focus on improving the accuracy of recognition methods, the image quality is essential to the effectiveness of the algorithm. However, evaluating the quality of crack images has received little attention in computer‐aided civil and infrastructure engineering. A prominent issue is whether surface cracks are visible and measurable in images. This study proposes an image quality evaluation method using an original standard test chart that simulates cracks of different widths and directions. Geometric transformations and preprocessing techniques are employed in a full‐reference strategy to process the acquired crack images. The resulting information provides quantitative scores for crack visibility and measurability. The proposed Crack Structural Similarity Index is more in line with human perception and offers an accurate evaluation of real image quality. The study shows that Gaussian blur disturbance and random noise disturbance primarily affect measurability and visibility, respectively. Furthermore, the study finds that the quality of the crack image improves with increasing sensor pixel size and using a prime lens over a zoom or long zoom lens. This approach enables comparing image quality collected by different devices in the field environment and provides guidance for optimizing field acquisition parameters. In the future, the results of this study can be applied to facilitate the application of automated testing equipment and improve overall performance. [ABSTRACT FROM AUTHOR]

The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility. [ABSTRACT FROM AUTHOR]

As robot technologies are rapidly improving, an increasing number of new ideas on utilizing robots for automated operation and maintenance tasks in nuclear power plants (NPPs) are being studied. However, due to safety concerns, researchers hardly found opportunities to test their new robot solutions on physical NPPs. In that sense, an efficient and realistic simulation environment plays a vital role in the development of automation systems for an NPP. In this paper, we propose the design of a 3D digital twin system capable of simulating NPP in real-time. This system obtains the data from a full-scope NPP simulator to reproduce the operating conditions of the plant. In addition, a scenario of a team of robots performing inspection tasks like temperature and pressure measurements will highlight its usability. This system enables development of intelligent robot swarms to deploy for inspection and maintenance purposes. It will positively impact autonomous control and operations for many types of reactors by reducing uncertainty in autonomous control and providing the tools necessary for remote intervention. [ABSTRACT FROM AUTHOR]

One of the principal sources of pollution, on a local scale for a water city, with a tourist and commercial port, is certainly the port. Monitoring what is happening here is essential in order to implement suitable measures to control and contain emissions with consideration for the increasingly delicate environmental problem. This paper details the methods and results of an experimental campaign of local-scale emission measurements conducted in the port of Naples for two weeks in 2021. The chosen instrumentation, its setup, post-processing of the data, and an analysis critique of the results will be presented in detail. The campaign is part of broader research attempting to superimpose the concentrations of pollutants measured ashore in the port area with what is emitted by moored ships. [ABSTRACT FROM AUTHOR]

HUMS (Health and Usage Monitoring Systems) provide enhanced safety and availability by alerting maintenance personnel when components (shaft/gears/bearings) have degraded or become damaged. Proactive maintenance ensures that a degraded component will not fail in flight. Often, the damage is from high cycle fatigue or other relatively slow degradation processes. However, some events, such as maintenance, result in a step-change in the component's health. While high cycle fatigue degradation can be trended, a step-change in component health presents a challenge. This paper describes the development of two methods for step-change detection. These methods would allow the automated capture of maintenance or other events resulting in a step-change in component health. [ABSTRACT FROM AUTHOR]

To meet the requirements for automated testing during equipment maintenance for odometers in urban rail transit, this paper first compares different measurement methods of odometers, and then proposes a quick measurement method of odometers that is suitable for field maintenance. It also makes the proposal that, to improve the accuracy of the test results of odometers, statistical analysis of their dynamic performance indicators should be performed, rather than testing and analysis of their static performance indicators. The proposed quick measurement method of odometers has been verified through prototype testing and put into practical application, and has produced good application results. [ABSTRACT FROM AUTHOR]

Space domain systems must go through different types of ground testing. For system-level black-box functional testing, ground support equipment is built ad hoc, customized for each different mission. Building any of this specific equipment involves considerable engineering effort that can be diluted using techniques that allow reusing configurations of the test setup environment without recodification. These techniques can be merged into a hierarchical checking process based on independent filters to compare the received outputs with the expected ones. The hierarchical checking allows the separate definition of several layers or levels of validation, from the lowest protocol packet levels to the logical abstractions at the highest application level. This paper introduces a solution based on Model-Driven Engineering for Low-Code Ground Support Equipment. It uses the abovementioned mechanisms to reduce the effort to develop and customize ground support systems for different missions. This solution is integrated within an environment called MASSIVA, which allows the automatic configuration and definition of system-level test procedures. This environment has been used in the software verification and validation process of the Instrument Control Unit of the Energetic Particle Detector on board Solar Orbiter. • Low-Code solution for Ground Support Equipment development. • Model-Driven Engineering support for black-box system-level test definition. • Automatic checking process based on hierarchical definition of independent filters. [ABSTRACT FROM AUTHOR]

To ensure the safety of a concrete structure, periodic and accurate inspection for damage is necessary. However, there is a high risk of inaccurate diagnosis of the structure condition because the manual inspection method is dependent on operator experience and subjective judgment. Additionally, in future society, it may become increasingly difficult to maintain high‐quality infrastructure, as the number of inspection personnel will also decrease with a decrease in population. For this purpose, the demand for accurate and automated inspection technology is increasing. To meet these issues, in this study, an objective and automated inspection method is proposed by developing an inspection robot and management system. The inspection robot comprises an artificial intelligence sensor, a manipulator, and a ground vehicle; it can autonomously drive inside a tunnel and inspect the damage on concrete surfaces using stereo vision. The management system remotely controls the robot through wireless communication and monitors the inspection status in real time. In addition, damage is automatically restored in three dimensions based on the images, and the physical size of the damage is analyzed with an average relative error of 0.39%. This method is expected to be used as a core technology for unmanned and automated tunnel maintenance in the future. [ABSTRACT FROM AUTHOR]

With the development of the digital and intelligent transformation of the power grid, the structure and operation and maintenance technology of the power grid are constantly updated, which leads to problems such as difficulties in information acquisition and screening. Therefore, we propose a recommendation method for power knowledge retrieval based on a graph neural network (RPKR-GNN). The method first uses a graph neural network to learn the network structure information of the power fault knowledge graph and realize the deep semantic embedding of power entities and relations. After this, it fuses the power knowledge graph paths to mine the potential power entity relationships and completes the power fault knowledge graph through knowledge inference. At the same time, we combine the user retrieval behavior features for knowledge aggregation to form a personal subgraph, and we analyze the user retrieval subgraph by matching the similarity of retrieval keyword features. Finally, we form a fusion subgraph based on the subgraph topology and reorder the entities of the subgraph to generate a recommendation list for the target users for the prediction of user retrieval intention. Through experimental comparison with various classical models, the results show that the models have a certain generalization ability in knowledge inference. The method performs well in terms of the MR and Hit@10 indexes on each dataset, and the F1 value can reach 87.3 in the retrieval recommendation effect, which effectively enhances the automated operation and maintenance capability of the power system. [ABSTRACT FROM AUTHOR]

Agrivoltaics power generation is the simultaneous use of agricultural land and photovoltaic panels. In such cases, the panels are placed more sparsely, compared to conventional photovoltaic plants. Furthermore, the panels might be mounted at higher heights, to provide the required space for the farm. Due to this arrangement of the panels in wide areas with crops on the farm, maintenance of the panels is a hard task. The major part of maintenance is to clean the panels, since the accumulation of farm dust and bird excrement can reduce the efficiency of the panels. In Agrivoltaics plants, the panels can be scattered, thus it is not economical for each panel to have a dedicated cleaning robot. This paper presents the initial design and analysis of an automated system for cleaning such power plants. This system consists of a robotic AGV, which transfers a panel cleaner between the photovoltaic panels mounted over the farms. The initial design is presented. Then, to anticipate the required power and control system, the carrier kinetics and kinematics are modeled and validated through simulations. Then, position and trajectory controllers are designed and simulations are presented. The simulations show desired performance for the introduced controlled system. [ABSTRACT FROM AUTHOR]

In the past 20 years, semiconductor manufacturing technology has advanced rapidly, but the advancement of integrated circuit (IC) testers has been slow. Using obsolete testers to inspect advanced wafers has become a significant challenge for test manufacturers. In this research, we used DITM (digital IC testing model) to discuss the impact of the test guardband (TGB) on quality and yield. Considering the interaction between semiconductor fabrication capability parameters and test capability parameters, we proposed an estimation method [deductive estimation method (DEM)] to analyze the electrical distribution changes of products after chip production and deduce the yield of future products. The deductive estimation method can correctly depict the future test yield (Y t) curve using the chip frequency data published by IRDS (International Roadmap for Devices and Systems) in 2017. Furthermore, test manufacturers can measure whether the current test capabilities can cope with future semiconductor chip manufacturing capabilities by predicting the trends. Next, test manufacturers can maintain high-quality and high-yield chip output by pre-adjusting the hardware testing capabilities of ATE (automated test equipment) or proposing more effective chip testing methods. [ABSTRACT FROM AUTHOR]

Technology can have a positive impact on various fields, including agriculture. By integrating technology, agricultural practices can be automated, specifically in plant maintenance management systems, simplifying the process of growing and caring for plants. In the context of automated plant maintenance and growth, the Green House method incorporates factors such as humidity, temperature, and illumination. To facilitate faster and more effective plant cultivation and care, this study proposes an intelligent plant system that aims to promote plant growth. The data collected by connected sensors is gathered and interpreted using Arduino, enabling the generation of recommendations for greenhouse plant maintenance. The sensor's output properties demonstrate its capability in supporting the objectives. [ABSTRACT FROM AUTHOR]

In this study, we develop a digital integrated circuit testing model (DITM) based on a statistical simulation method to evaluate the test quality and yield of integrated circuit products. This model can be used to quantify the characteristics of the device under test (DUT) and simulate the effect of the test guardband (TGB) on test results during testing. The complexity and functionality of integrated circuits have continued to increase over the past two decades. Moreover, the development in speed of automated test equipment (ATE), e.g., OTA or overall timing accuracy, according to the ITRS report, lags behind the progress of semiconductor manufacturing. Hence, using existing instruments and tools to select zero-defect products would be a considerable challenge for suppliers due to the slow development of the testing technology. We propose a new scheme of using multiple retest systems (MRSs) to improve the yield while maintaining the desired quality to address the product quality requirements of consumers. We also use a set of parameters from IRDS 2021 (International Roadmap for Devices and Systems 2021) to estimate the future test yield (Yt) and test quality through DITM calculations. MRS results showed that the test yield (Yt) can be improved while achieving the expected quality. MRSs not only improve the performance of the tester but also demonstrate effective performance in the yield improvement of high-quality products. This approach enables high-quality, high-yield chip delivery, and significantly increases the overall profit of the company. [ABSTRACT FROM AUTHOR]

5G heterogeneous networks (HetNets) can provide higher network coverage and system capacity to the user by deploying massive small base stations (BSs) within the 4G macrosystem. However, the large-scale deployment of small BSs significantly increases the complexity and workload of network maintenance and optimisation. The current handover (HO) triggering mechanism A3 event was designed only for mobility management in the macrosystem. Directly implementing A3 in 5G-HetNets may degrade the user mobility robustness. Motivated by the concept of self-organisation networks (SON), this study developed a self-optimisation triggering mechanism to enable automated network maintenance and enhance user mobility robustness in 5G-HetNets. The proposed method integrates the advantages of subtractive clustering and Q-learning frameworks into the conventional fuzzy logic-based HO algorithm (FLHA). Subtractive clustering is first adopted to generate a membership function (MF) for the FLHA to enable FLHA with the self-configuration feature. Subsequently, Q-learning is utilised to learn the optimal HO policy from the environment as fuzzy rules that empower the FLHA with a self-optimisation function. The FLHA with SON functionality also overcomes the limitations of the conventional FLHA that must rely heavily on professional experience to design. The simulation results show that the proposed self-optimisation FLHA can effectively generate MF and fuzzy rules for the FLHA. The proposed approach can minimise the HO, ping-pong HO, and HO failure ratios while improving network throughput and latency by comparing with conventional triggering mechanisms. [ABSTRACT FROM AUTHOR]

Because of inspection errors, expensive items such as computer chips are usually inspected more than once with the same testing device to further improve the quality of accepted items. Many researchers have considered various multiple inspection plans that minimize the expected total cost of inspection and misclassifications. We first propose a new Markovian inspection plan under which each item is tested repeatedly until we have a sufficient number of positive or negative test results. We then deal with the problem of estimating three model parameters: the type I and II errors of an automated test equipment and the fraction defective of incoming items. Because of computational difficulties in maximizing the likelihood of the three parameters, we propose the use of the expectation-maximization (EM) algorithm as an easy alternative. In a numerical analysis, we demonstrate the outstanding performance of our new inspection plan over previous ones. [ABSTRACT FROM AUTHOR]

Higher complexity in recent chip designs, module integration, and increasing test quality requirements have expanded measurement needs and further increased chip test costs. Multi-site testing (parallel measurement) solves this issue by taking test measurements from multiple chips simultaneously, massively increasing throughput, and significantly reducing the test time per chip. Massive multi-site testing system, a setup with significant measurement site count, further improves throughput and maximizes gains. However, it unavoidably amplifies site-to-site variations in the measured specifications. This problem is particularly magnified in analog and mixed-signal chips. Some measurement sites now exhibit pronounced induced errors, and their measurements no longer reflect the actual performance of the device under test (DUT). This problem presents a solid need to identify sites that suffer from extreme site-to-site variations (issue sites). We propose an automated method to investigate site-to-site variations in volume multi-site data and identify issue sites that may not be obvious via human inspection or basic statistical methods. Assuming that all measurement sites have the same accuracy and precision, we consider an issue site to be one whose weighted-bin difference score is greater than an analytically derived upper bound. We apply the proposed method to simulation data and volume test data obtained from an industrial analog and mixed-signal system on chips (SoCs) that were tested using multi-site testing hardware and show that the technique can effectively identify issue sites in the testing system. We compare the proposed algorithm to existing methods and demonstrate its superior performance. [ABSTRACT FROM AUTHOR]

This article presents a novel built-in test equipment (BITE) for phase measurements in millimeter-wave integrated circuits (ICs). The BITE targets 5G New Radio (NR) applications. It is able to measure the phase in good agreement with $\mathbf {S_{21}}$ measurements and has a relative rms phase error lower than 6° over the frequency band of interest. Aside from the relative phase, this BITE also addresses the absolute phase difference of all ICs on the same phased array. To the authors’ best knowledge, this is the first BITE and built-in self-test (BIST) to do so. The BITE is able to reduce the absolute phase discrepancy by a factor of 3. To reduce the measurement complexity, the BITE is implemented as a homodyne architecture to output a dc voltage relative to the phase of the channel. A built-in algorithm is used, mitigating the impairments normally associated with a homodyne receiver. This reduces the design complexity and hence the area overhead. The BITE occupies an area of 480 $\mathbf {\mu m} \times 135\,\,\mathbf {\mu m}$ , facilitating easy integration. [ABSTRACT FROM AUTHOR]

Development of an Automated Test System (ATS) is a process that involves extensive study and knowledge of current test technologies, determination of the requirements, and a simple design approach. Communication payload architecture has changed from broad beam to spot beam technology, providing more bandwidth and power. As the number of transponders increases, the conventional way of testing payload requires more time; this, in turn, increases total cost, specifically thermal-vacuum test. [ABSTRACT FROM AUTHOR]

Regular inspection and maintenance can ensure safe working conditions of transport pipelines without leakage and damage. Pipeline-climbing robots can be used for rapid inspection of pipelines, effectively reducing labor costs and time consumption. For the annular pipelines outside spherical tanks, the special distribution and installation form presents more high obstacles, and puts forward higher requirements for the robot's climbing performance and obstacle-surmounting ability. An elastic obstacle-surmounting pipeline-climbing robot with composite wheels is proposed in this paper. The designed elastic shock-absorbing suspension mechanisms and composite wheels were designed to increase the stability and obstacle-surmounting ability of the robot. The adjustable robot frame and rotating joint mechanisms allowed the robot to adapt to pipelines of different diameters and radians. Force analysis and simulation of obstacle surmounting by the robot were performed. Experiments were conducted on a 110-mm diameter pipeline to test the payload performance and obstacle-surmounting ability of the robot. With its elastic shock-absorbing suspension mechanisms, the pipeline-climbing robot could carry a 30 kg payload and stably climb the pipeline. The maximum height of obstacles surmounted by the composite wheels of the robot was 20 mm. In the process of surmounting obstacles, the velocity and inclination angle of the robot could remain relatively stable. This novel composite wheels and mechanisms can improve the performance of the pipeline-climbing robot and solve the problem of surmounting high obstacles. By carrying various equipment and instruments, the robot can promote the automated maintenance and inspection of complex pipelines. [ABSTRACT FROM AUTHOR]

With the improvement of System-on-Chip integration, the chip requires an increasingly large amount of test data. To solve the contradiction between the storage capacity and bandwidth of automatic test equipment (ATE), a new method of test data compression/decompression is proposed based on an annular scan chain. Corresponding fault bits of different test patterns are incompatible, moving test patterns in an annular scan chain, makes all of the new corresponding bits of different test patterns be compatible or backward-compatible, so different adjacent test patterns form a new relation that are indirectly compatible or indirectly backward-compatible, achieves the purpose of test data compression by encoding these indirectly compatible test patterns or indirectly backward-compatible test patterns. According to experimental results, the average compression ratio increases by %6.94 to % 15.1 compared with the other schemes, relative decompression architecture is simple. In the annular scan chain, the test pattern moves clockwise with the minimal bits, generating subsequent test patterns quickly, it is advantageous to reduce the test application time of a single IP core. [ABSTRACT FROM AUTHOR]