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We introduce a new carry look-ahead adder (NCLA) architecture that employs non-uniform-size carry look-ahead adder (CLA) modules, in contrast to the conventional CLA (CCLA) architecture, which utilizes uniform-size CLA modules. We adopted two strategies for the implementation of the NCLA. Our novel approach enables improved speed and energy efficiency for the NCLA architecture compared to the CCLA architecture without incurring significant area and power penalties. Various adders were implemented to demonstrate the advantages of NCLA, ranging from the slower ripple carry adder to the widely regarded fastest parallel-prefix adder viz. the Kogge–Stone adder, and their performance metrics were compared. The 32-bit addition was used as an example, with the adders implemented using a semi-custom design method and a 28 nm CMOS standard cell library. Synthesis results show that the NCLA architecture offers substantial improvements in design metrics compared to its high-speed counterparts. Specifically, an NCLA achieved (i) a 14.7% reduction in delay and a 13.4% reduction in energy compared to an optimized CCLA, while occupying slightly more area; (ii) a 42.1% reduction in delay and a 58.3% reduction in energy compared to a conditional sum adder, with an 8% increase in the area; (iii) a 14.7% reduction in delay and a 37.7% reduction in energy compared to an optimized carry select adder, while requiring 37% less area; and (iv) a 20.2% reduction in energy and a 55.4% reduction in area compared to the Kogge–Stone adder. [ABSTRACT FROM AUTHOR]

Nowadays, the application of computations and communications is needed for high performance, reduced size and lower power utilisation. The multiply and add functions are one of the frequently used operations in digital signal processing. Various types of multipliers are available in digital Various types of multipliers are available for various Signal processing applications.. Among these multipliers, Vedic multiplier is one of the most optimised multipliers used in a signal processing module. In the existing method, the Vedic multiplier is designed with conventional adders, which is having higher area utilisation, lower speed and higher power consumption. Hence, the modified Vedic multiplier is proposed to improve the speed of multiplication using hybrid technology. The partial products of the proposed multiplication are added using 2 × 2 Vedic multiplier and hybrid carry select adder (binary to excess one converter (BEC), Han-Carlson adder and Multiplexer). The critical path delays of hybrid 4 × 4 Vedic multiplier are the summation of 2 × 2 Vedic multiplier, two full adders, two multiplexers and two BECs for producing the final product. The proposed hybrid Vedic multiplier is operated at high speed with reduced size as compared to the existing multiplier techniques. The proposed hybrid Vedic multiplier is designed and simulated using Verilog HDL and implemented in Spartan 6 field-programmable gate array device. The implementation results showed that the delay of the proposed multiplier gets ameliorated as compared to array multiplication (30.84%), Wallace tree multiplication (29.52%), multiplication based on compressor (23.71%), Vedic multiplication by carry look-ahead adder (22.91%), Vedic multiplication by ripple carry adder (14.45%), revised booth multiplication (15.42%) and Vedic multiplication by Han-Carlson adder with BEC (13.95%) and hybrid multiplier (11.37%). [ABSTRACT FROM AUTHOR]

Traditional logic circuit emits energy into the environment due to information loss, and it is referred to be irreversible logic circuits. Reversible logic circuit is capable of diminishing power loss, quantum cost, and garbage output. Many academics have recently embraced reversible logic-based circuits exploiting all-optical technology to conduct their research. In this article, all-optical reversible adder and subtractor have been implemented using microring resonator-based Naveen Raymond reversible logic gate, for the first time to our knowledge. MATLAB serves as the tool for design and analysis of the proposed architecture at almost 260 Gbps operational speed. The ultrafast response times and compact design of the microring resonator-based circuits make them especially useful for digital signal processing and communication systems. Some performance reflecting factors such as "quality factor", "photon cavity lifetime", "extinction ratio", "contrast ratio", "amplitude modulation", "on-off ratio", and "relative eye opening" are explored and analyzed. Optimized design parameters have been selected in order to build the model practically. [ABSTRACT FROM AUTHOR]

In this paper, a new structure for a 1-bit full adder is proposed based on dynamic logic methodology, which utilises pass transistors. The clocking operation falls into two phases. The clocking operation consists of a pre-discharged cycle, during which pseudo capacitors are reset to zero when the clock signal is high, and an evaluation cycle, during which the circuit outputs the adder function when the clock signal is low. The circuit uses a combination of 12 pass-transistors to better implement the full adder logic function with the maximum of a NMOS threshold voltage drop. Moreover, the circuit has no direct connection to the power-supply node and so this can possibly save the power dissipation. Our new adder outperforms other 1-bit full adder structures in terms of power-delay factor, according to simulation results. [ABSTRACT FROM AUTHOR]

We propose schemes for binary adder, subtractor and parity checker using optical logic gates. These schemes could be useful for calculations using optical systems. Utilizing optical logic gates, we can achieve functions of binary adder, subtractor and parity checker of high-speed optical signals. Due to two-photon absorption in the wetting layer, quantum dot-semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA-MZI) can work as high data rate optical logic gates. The simulated result supports the idea that it is possible to realize all-optical binary adder, subtractor and parity checker at high optical signal rates. [ABSTRACT FROM AUTHOR]

Processing in Memory based on memristors is considered the most effective solution to overcome the Von Neumann bottleneck issue and has become a hot research topic. The execution efficiency of logical computation and in-memory data transmission is crucial for Processing in Memory. This paper presents a design scheme for data transmission and multi-bit multipliers within MAT (a data storage set in MPU) based on the memristive alternating crossbar array structure. Firstly, to improve the data transfer efficiency, we reserve the edge row and column of the array as assistant cells for OR AND (OA) and AND data transmission logic operations to reduce the data transfer steps. Furthermore, we convert the multipliers into multi-bit addition operations via Multiple Input Multiple Output (MIMO) logical operations, which effectively improves the execution efficiency of multipliers. PSpice simulation shows that the proposed data transmission and multi-bit multiplier solution has lower latency and power consumption and higher efficiency and flexibility. [ABSTRACT FROM AUTHOR]

This paper proposed the design and development of reversible cost-efficient innovative quantum dual-full adder and subtractor or QD-FAS circuit using quantum gate. The proposed circuit can be used as full adder and full subtractor simultaneously, which is designed using double Peres gate or DPG and Feynman gate or FG. The quantum cost, garbage output and constant input of the QD-FAS is 8, 1 and 1. Which is better w.r.t previously reported work. The QD-FAS circuit, as proposed, includes shared sum and difference terminals, as well as a carry-out and a borrow output terminal. Notably, this innovation showcases a remarkable 27.27% reduction in quantum cost. The improvement in garbage output is even more striking, showing a 50% enhancement. When assessing the overall advancement in quantum cost, it falls within the range of 27.27% to 66.66%. To confirm the viability of this design, extensive testing is carried out using the IBM Qiskit simulator. This design holds significant importance in a variety of applications, including quantum computing, cryptography, and the realm of reversible Arithmetic Logic Units (ALU).

Purpose: In radiology, several medical imaging modalities were used. In recent Biomedical systems, integrated circuits were used in the form of Application Specific Integrated Circuits (ASICs) to perform FFT. The raw data obtained from the acquiring equipment are reconstructed to image using Fast Fourier Transform (FFT). The contribution in the paper is to design an FFT integrated unit for converting the Magnetic Resonance (MR) signal into frequency spectrum of each phase encoding. Materials and Methods: The image created is been transformed from the spatial projection using inverse Fourier transform. The k-space FFT information were back projected to obtain the MRI image. This paper presents an integrated circuit implementation of FFT processing elements used in Magnetic Resonance Imaging (MRI) reconstruction and ultrasonic imaging. The circuits designed in this work is to be used in the back-projection unit of MRI reconstruction. The complex periodic signal received from the receiver coils in MRI or piezoelectric disc in ultrasound and detector array in CT are analyzed using Fourier transform. The proposed single-path delay feedback (SDF) Decimation In Frequency (DIF) 4096-point FFT for image reconstruction was implemented in 65nm FPGA kit and programmed using VHDL in Quartus tool. Results: This block becomes the part of the reconstruction unit of MRI image. The proposed design reduces the execution of instruction per cycle and the fixed point arithmetic provides low roundoff error. Conclusions: Since in MRI reconstruction the frequency encoding and phase encoding is combined to develop the images the proposed FFT will be useful. In Future application specific integrated circuits will be designed for the entire MRI back projection and reconstruction unit. [ABSTRACT FROM AUTHOR]

This paper proposed the design and development of reversible cost-efficient innovative quantum dual-full adder and subtractor or QD-FAS circuit using quantum gate. The proposed circuit can be used as full adder and full subtractor simultaneously, which is designed using double Peres gate or DPG and Feynman gate or FG. The quantum cost, garbage output and constant input of the QD-FAS is 8, 1 and 1. Which is better w.r.t previously reported work. The QD-FAS circuit, as proposed, includes shared sum and difference terminals, as well as a carry-out and a borrow output terminal. Notably, this innovation showcases a remarkable 27.27% reduction in quantum cost. The improvement in garbage output is even more striking, showing a 50% enhancement. When assessing the overall advancement in quantum cost, it falls within the range of 27.27% to 66.66%. To confirm the viability of this design, extensive testing is carried out using the IBM Qiskit simulator. This design holds significant importance in a variety of applications, including quantum computing, cryptography, and the realm of reversible Arithmetic Logic Units (ALU). [ABSTRACT FROM AUTHOR]

Masking is a promising countermeasure against side-channel attacks, and share slicing is a masking technique that stores all shares in a single register to exploit the parallelism of Boolean instructions. However, the security of share slicing relies on the assumption of bit-independent leakage. Gao et al. recently discovered that bit-interaction leakage causes security degradation by experimentally evaluating ARM processors. However, its causality remains an open question because of the black box nature of the target processors. In this study, we approach this problem with simulation-based side-channel leakage evaluation using a RISC-V processor. More specifically, we use Western Digital's open-source SweRV EH1 core as a target platform and measure its side-channel traces by running logic simulation and counting the number of signal transitions in the synthesized netlist. We successfully replicate the bit-interaction leakage from a shifter using the simulated traces. By exploiting the flexibility of simulation-based analysis, we positively verify Gao et al.'s hypothesis on how the shifter causes the leakage. Moreover, we discover a bit-interaction leakage from an arithmetic adder caused by carry propagation. Further, we discuss hardware and software countermeasures against bit-interaction leakage. [ABSTRACT FROM AUTHOR]

This research aims to fill up the research gap in energy‐efficient transistor‐level wide word‐length carry circuit generator by using ripple carry (RC) and carry look‐ahead (CLA) method‐based hybrid 4‐bit carry generation process for wide word‐length carry‐select adder (CSLA). Compared to the existing 4‐bit CLA architectures, the proposed 4‐bit RC‐CLA method‐based hybrid 4‐bit carry generator showed performance improvement in terms of power and power delay product (PDP). Later, the 4‐bit carry architectures (existing and proposed) were used as a base to implement 16‐bit carry select adder (CSA) in order to investigate and compare the effect of using the proposed hybrid RC‐CLA based 4‐bit carry generator in large structures. Unlike 4‐bit operation, the proposed design displayed the best performance in power and PDP for 16‐bit CSA extension, which proves its effectiveness in wide word‐length adder structures. [ABSTRACT FROM AUTHOR]

As the semiconductor industry continues to decrease in size, it faces many issues, such as scalability, leakage, short-channel effects, and reliability. carbon nanotubes (CNT) has become a potential new technology that can address the shortcomings of CMOS without compromising both performance and reliability. The research presents the design, simulation, and comparison of an improved full-swing 11 Transistor (11T) adder based on CNT with a CMOS implementation in the 32 nm technological node. The CNT-based adder demonstrated superior performance compared to CMOS-based equivalents in terms of power consumption and delay, along with the power-delay product (PDP). The CNTFET adder demonstrates a minimum power consumption reduction of 73 %, a minimum decrease in delay of 29 %, and a minimum reduction in the power-delay product (PDP) of 81 % when compared to the CMOS version of the adder with supply voltage ranging from 0.8 V to 1.2 V. The CNTFET adder demonstrates a minimum power consumption reduction of 64 %, a minimum decrease in delay of 19 %, and a minimum reduction in the power-delay product (PDP) of 71 % when compared to the CMOS version of the adder with temperature ranging from -25 °C to 75 °C.

Online arithmetic, where computations are performed from the most significant digit first, has shown benefits in improving throughput and latency within high-performance computing. This computational mode is particularly beneficial for intensive data processing in sequential operations, enabling streaming computations. One such intensive operation is sparse matrix-vector multiplication (SpMV) which finds extensive application in various engineering fields. SpMVs are often carried out in compressed formats such as coordinate encoding format that inherently follows a sequential approach to execute multiply-and-accumulate (MAC) operations of sparse elements. Therefore, this paper proposes an online MAC unit, through a novel algorithm and architecture. Moreover, a SpMV unit is developed by integrating the proposed online MAC unit. The performance and efficiency of the proposed MAC design are evaluated against state-of-the-art MAC designs, synthesized using the TSMC 45 nm CMOS standard cell library with the Synopsis Design Compiler. Results demonstrate the superiority of the proposed MAC unit in terms of delay, area-delay product, and energy consumption. Besides, the SpMV employing the online MAC is compared with counterpart SpMV designs implemented in both ASIC and FPGA. The proposed SpMV design outperforms conventional designs in various performance metrics, achieving a speed-up of $1.69\times $ and energy reductions of up to 60.4% compared to other SpMV designs for 8-bit precision. Moreover, various sparse matrix datasets with different properties are used to evaluate the SpMV using the online MAC unit, considering metrics such as power, delay, hardware resources, and energy consumption.

Encryption algorithms work with very large key values to provide higher security. In order to process high-capacity data in real-time, we need advanced hardware structures. Today, when compared to the previous designing methods, the required hardware solutions can be designed more easily by using Field Programmable Gate Array (FPGA). Over the past decade, FPGA speeds, capacities, and design tools have been improved. Thus, the hardware that can process data with high capacity can be designed and produced with lower costs. The purpose of this study is to create the components of a high-speed arithmetic unit that can process high-capacity data, which can also be used for FPGA encoding algorithms. In this study, multiplication algorithms were analyzed and high-capacity adders that constitute high-speed multiplier and look-up tables were designed by using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. The simulation results were obtained through ModelSIM and ISIM programs.

Abstract Adder ( Vipera berus ) populations are experiencing declines in many countries, including the United Kingdom. Perceptions of adders and other venomous snakes are generally negative, making conservation of these species a challenge, and persecution remains within the top five perceived causes for adder declines in the United Kingdom. Improved understanding and attitudes are needed to support current conservation efforts. However, ensuring these positive attitudes continue into the future relies on addressing children's loss of connection to nature, and intervention at this early attitude‐formation stage can be crucial for traditionally ‘unpopular’ species, such as snakes. An adder‐focussed public engagement project, Adders are Amazing !, was carried out in Pembrokeshire, United Kingdom, in 2018–19 to improve understanding and attitudes towards adders using a blended science‐creative arts approach. The project included half‐day primary school‐based workshops to inform 111 pupils aged 8–11 about adder ecology, alongside creative art experiences. Questionnaires were used to measure the children's attitudes towards adders and their nature connectedness both before and after the workshops and these were compared with equivalent questionnaires carried out at a control school (57 pupils) where no workshops were conducted. The project demonstrated that engagement that blends both art and science can significantly change attitudes towards adders without any direct contact with the animals themselves; specifically, participants' scores for ‘Wonder’, ‘Learning Interest’ and ‘Conservation Concern’ increased. The workshops also significantly increased measures of the children's general connectedness to nature (specifically, ‘Enjoyment of Nature’ and ‘Responsibility for Nature’). We recommend conservation bodies focus on, and not shy away from, so‐called ‘unpopular’ species, to promote understanding and acceptance of these species and support their conservation. Blended arts–science initiatives, which can be easily adapted to suit a wide range of species and the artistic practices of local communities, are an effective way to achieve this. Read the free Plain Language Summary for this article on the Journal blog.

Encryption algorithms work with very large key values to provide higher security. To process high-capacity data in real time, we need advanced hardware structures. Today, compared to previous design methods, hardware solutions can be designed more easily using Field-Programmable Gate Arrays (FPGAs). Over the past decade, FPGA speeds, capacities, and design tools have been improving. Thus, the hardware that can process high-capacity data can be designed and produced with lower costs. This study aims to create the components of a high-speed arithmetic unit that can process high-capacity data and be used for FPGA encoding algorithms. In this study, multiplication algorithms were analyzed. High-capacity adders that constitute high-speed multiplier and look-up tables were designed using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. Simulation results were obtained using the ModelSIM and ISIM programs. [ABSTRACT FROM AUTHOR]

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After almost a decade of research, development of more efficient imprecise computational blocks is still a major concern in imprecise computing domain. There are many instances of the introduced imprecise components of different types, while their main difference is that they propose different precision-cost-performance trade-offs. In this paper, a novel comprehensive model for the imprecise components is introduced, which can be exploited to cover a wide range of precision-cost-performance trade-offs, for different types of imprecise components. The model helps to find the suitable imprecise component based on any desired error criterion. Therefore, the most significant advantage of the proposed model is that it can be simply exploited for design space exploration of different imprecise components to extract the suitable components, with the desired precision-cost-performance trade-off for any specific application. To demonstrate the efficiency of the proposed model, two novel families of Lowest-cost Imprecise Adders (LIAs) and Lowest-cost Imprecise Multipliers (LIMs) are introduced in the paper, which are systematically extracted based on exploration of the design space provided by the proposed model. A wide range of simulation and synthesis results are also presented in the paper to prove the comparable efficiency of the systematically extracted LIA/LIM structures with respect to the most efficient existing human-made imprecise components both individually and in a Multiply-Accumulate application. [ABSTRACT FROM AUTHOR]

Abstract This research aims to fill up the research gap in energy‐efficient transistor‐level wide word‐length carry circuit generator by using ripple carry (RC) and carry look‐ahead (CLA) method‐based hybrid 4‐bit carry generation process for wide word‐length carry‐select adder (CSLA). Compared to the existing 4‐bit CLA architectures, the proposed 4‐bit RC‐CLA method‐based hybrid 4‐bit carry generator showed performance improvement in terms of power and power delay product (PDP). Later, the 4‐bit carry architectures (existing and proposed) were used as a base to implement 16‐bit carry select adder (CSA) in order to investigate and compare the effect of using the proposed hybrid RC‐CLA based 4‐bit carry generator in large structures. Unlike 4‐bit operation, the proposed design displayed the best performance in power and PDP for 16‐bit CSA extension, which proves its effectiveness in wide word‐length adder structures.

Processing in Memory based on memristors is considered the most effective solution to overcome the Von Neumann bottleneck issue and has become a hot research topic. The execution efficiency of logical computation and in-memory data transmission is crucial for Processing in Memory. This paper presents a design scheme for data transmission and multi-bit multipliers within MAT (a data storage set in MPU) based on the memristive alternating crossbar array structure. Firstly, to improve the data transfer efficiency, we reserve the edge row and column of the array as assistant cells for OR AND (OA) and AND data transmission logic operations to reduce the data transfer steps. Furthermore, we convert the multipliers into multi-bit addition operations via Multiple Input Multiple Output (MIMO) logical operations, which effectively improves the execution efficiency of multipliers. PSpice simulation shows that the proposed data transmission and multi-bit multiplier solution has lower latency and power consumption and higher efficiency and flexibility.

Recently, a growing focus has been on the need for ultra-low-voltage (ULV) functioning to reduce energy usage. The full adder is a fundamental computational arithmetic unit in various image and signal processing applications. This study presents a novel architectural design for a 1-bit adder that utilizes 10 transistors. The concept relies on an energy-efficient hybrid logic multiplexer approach incorporating Gate Diffusion Input (GDI) logic. The primary goal of the suggested design for a hybrid full adder is to decrease power consumption while concurrently decreasing the required area. The suggested innovative architectural design for a full adder incorporates level restoration carry logic and ensures a complete swing output voltage. The designs have been analyzed in a standard environment using 45-nm CMOS process technology, with various supply voltages utilized. The evaluation of the adder cells focuses on speed, power consumption, power-delay-product (PDP), and space efficiency compared to the existing full adders. The recommended full adder cells were subjected to comprehensive simulation tests utilizing the Mentor Graphics environment. The results suggest that these cells surpass their counterparts, exhibiting a minimum of 80 % enhancements in their power-delay product (PDP) parameters. Also the comparisons have been made between the proposed full adders with and without level restoration techniques. The proposed level restoration technique based full adder yields better performance in terms of power and delay when compared to proposed full adder without level restoration.

All-optical processor capable of processing optical bits has been a long-standing goal of photonics. In this paper, we report the results obtained by numerical simulations regarding the designing of an all-optical combinational circuit of an adder and subtractor circuits based on Si3N4 microring resonators. The designs of combinational circuit like adders and subtractor based on the use of all-optical basic logic gates are discussed while presenting the numerically simulated results. Extinction ratios of 5.2 dB, 3.5 dB and 2.7 dB are obtained for the half adder, full adder and half subtractor, respectively. [ABSTRACT FROM AUTHOR]

This article describes designing a low‐power novel circuit for overflow detection in two's complement arithmetic operations. The quantum‐dot cellular automata (QCA) is employed to achieve the nanoscale design. For designing the circuit of the proposed arithmetic overflow detector, a new layout of the QCA full adder is utilized. Two different designs of arithmetic overflow detectors are outlined in this article. The designs are compared based on latency, cell count, and device area. Based on the comparison, the best design for an arithmetic overflow detector is presented. The circuit cost for all the designs is also shown in this work. Besides, thermal power's effect on the output cell's polarization has also been investigated. The power dissipation of all proposed QCA layouts is estimated. [ABSTRACT FROM AUTHOR]

We examine five quantitative models of the cell-cycle and cell-size control in Escherichia coli and Bacillus subtilis that have been proposed over the last decade to explain single-cell experimental data generated with high-throughput methods. After presenting the statistical properties of these models, we test their predictions against experimental data. Based on simple calculations of the defining correlations in each model, we first dismiss the stochastic Helmstetter-Cooper model and the Initiation Adder model, and show that both the Replication Double Adder (RDA) and the Independent Double Adder (IDA) model are more consistent with the data than the other models. We then apply a recently proposed statistical analysis method and obtain that the IDA model is the most likely model of the cell cycle. By showing that the RDA model is fundamentally inconsistent with size convergence by the adder principle, we conclude that the IDA model is most consistent with the data and the biology of bacterial cell-cycle and cell-size control. Mechanistically, the Independent Adder Model is equivalent to two biological principles: (i) balanced biosynthesis of the cell-cycle proteins, and (ii) their accumulation to a respective threshold number to trigger initiation and division.

Big data applications involved with neural networks requires frequent data transfer between memory and processing elements and thus, take a significant portion of energy. One possible method is to realize logic operations inside the memory, often known as in-memory computing. The memristor employed in a crossbar can also conduct logic operations, making it a promising candidate for enabling such designs. In-memory computing can vastly improve speed efficiency by significantly reducing memory access time and energy. Therefore, efficient operations inside the memory are crucial for data-intensive applications. This article presents two high-speed adders in memristive technology, which are derived using IMPLY-based logic operations and can be implemented on a crossbar architecture for in-memory computing. One is a carry select adder, which uses efficient ripple carry adders and multiplexers. While the other is a conditional carry adder, designed using a modified half adder and multiplexers. An IMPLY-based multiplexer and modified half adder are proposed as part of these adders. A modified half adder calculates the sum of two inputs and two carry outputs for various carry inputs. Compared to conventional adder designs, the speed of these two adders has been significantly enhanced. In particular, the proposed 32-bit Carry Select Adder and Conditional Carry Adder take 123 and 90 computational steps, respectively. The proposed adders have improved the speed by 30% and 49%, respectively, compared to the best-existing adder in IMPLY. Further, this article presents computational steps and the number of memristors required for $n$ -bit adders. The proposed circuits were simulated using the VTEAM model, and energy consumed for each adder is calculated from the simulations. [ABSTRACT FROM AUTHOR]

Field Programmable Gate Arrays (FPGAs) are often used in space, military, and commercial applications due to their re-programmable feature. FPGAs are semiconductor components susceptible to soft errors due to radiation effects. Fault tolerance is a critical feature for improving the reliability of electronic and computational components in high-safety applications. Triple Modular Redundancy (TMR) is electronic systems' most commonly used fault-tolerant technique. TMR is reliable and efficient to recover the single-event upsets. However, the limitation of this technique is the area overhead. Prior work has proposed many conventional fault-tolerant approaches that have been unable to avoid area overhead. This paper introduces a novel work related to an error analysis-based technique. This technique works with an error percentage, and a preferential algorithm, which is also proposed to reduce the hardware complexity in the existing works. This technique can be applied on various types of arithmetic circuits. The proposed technique is applied to the adder circuit to verify the hardware usage, power consumption, and delay; it has been implemented on the Proasic3e 3000 FPGA. The simulated results were observed as 39.89% fewer IO cells, 47.10% fewer core cells, and 5.32% less power as compared to the TMR-based adder. [ABSTRACT FROM AUTHOR]

Quantum Dot-Cellular automata (QCA) is a developing technology that is considered as the best viable alternate solution for CMOS technology which has short-channel effects. QCA is a transistor-free technology, and the information is distributed formulated on the charge of the electron and by Columbic repulsion theory. In this paper, an optimal adder circuit is proposed using QCA technology which consist only 14 cells. The proposed adder circuit is further utilised for designing of 4-bit adder design efficiently. Simulations results, are obtained precisely using QCADesigner software version 2.0.3., confirm that the proposed circuits work well. Moreover, the energy dissipations of the proposed adder circuit design is estimated using QCAPro tool. The performance of the proposed design was compared with the existing ones which shows better performance in terms of cell count, area, and latency. Suggested 1-bit and 4-bit QCA adders exhibit a delay of 0.5 and 1.25 clock cycle, occupy an active area of 0.01 and 0.1 and μm2, and use 14 and 84 QCA cells, respectively. [ABSTRACT FROM AUTHOR]

Evolvable hardware-based fault-tolerant hardware design is an efficient approach to self-adaptability. It is an essential feature to mitigate errors on the fly. But there are two issues while designing an adder using the evolutionary hardware (EHW) approach: scalability issues in circuit representation and a low error recovery speed due to many evolutions. To avoid scalability issues, we designed an optimized virtual reconfiguration circuit (VRC) for adder. In this paper, we introduce the chromosome reconstruction algorithm for evolving the circuit to recover faults in an adder circuit at a faster speed. The proposed self-healing adder design is implemented on a single FPGA using an intrinsic approach. The complete hardware is designed on a Proasic A3PE3000 FPGA. Compared to existing work, the proposed work's resource utilization is optimal. [ABSTRACT FROM AUTHOR]

The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with highperformance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mantissa part of the RFP multiplier is created using a 24x24 Wallace tree multiplier. In contrast, the reciprocal unit of the RFP divider is designed using Newton Raphson’s method. The RFPA unit and its submodules are executed in parallel by utilizing one clock cycle individually. The RFPA unit and its submodules are synthesized separately on the Vivado IDE environment and obtained the implementation results on Artix-7 field programmable gate array (FPGA). The RFPA unit utilizes only 18.44% slice look-up tables (LUTs) by consuming the 0.891 W total power on Artix-7 FPGA. The RFPA unit sub-models are compared with existing approaches with better performance metrics and chip resource utilization improvements. [ABSTRACT FROM AUTHOR]

Evolutionarily divergent bacteria share a common phenomenological strategy for cell-size homeostasis under steady-state conditions. In the presence of inherent physiological stochasticity, cells following this "adder" principle gradually return to their steady-state size by adding a constant volume between birth and division, regardless of their size at birth. However, the mechanism of the adder has been unknown despite intense efforts. In this work, we show that the adder is a direct consequence of two general processes in biology: (1) threshold-accumulation of initiators and precursors required for cell division to a respective fixed number-and (2) balanced biosynthesis-maintenance of their production proportional to volume growth. This mechanism is naturally robust to static growth inhibition but also allows us to "reprogram" cell-size homeostasis in a quantitatively predictive manner in both Gram-negative Escherichia coli and Gram-positive Bacillus subtilis. By generating dynamic oscillations in the concentration of the division protein FtsZ, we were able to oscillate cell size at division and systematically break the adder. In contrast, periodic induction of replication initiator protein DnaA caused oscillations in cell size at initiation but did not alter division size or the adder. Finally, we were able to restore the adder phenotype in slow-growing E. coli, the only known steady-state growth condition wherein E. coli significantly deviates from the adder, by repressing active degradation of division proteins. Together, these results show that cell division and replication initiation are independently controlled at the gene-expression level and that division processes exclusively drive cell-size homeostasis in bacteria. VIDEO ABSTRACT.

The design of a full adder involves the use of logic gates so that the design can convert 8 inputs to create a byte-wide adder and to force the carry bit to the other adder. However, the uses of multiplexers to replace the logic gates in the construction of the full adder is proven to be possible due to the function of the multiplexers to act as the digital switch in the system that provides the flow of digital information from multiple inputs into an output. This research aims to explore the possibility of implementing the multiplexers into the design of the full adder and to analyse the different possible full adder design using the multiplexers. Using the multiplexers also allows for fewer logic gates to be used in the design of the full adder, which reduces the overall area coverage of the full adder. However, adding multiplexers does not make a complete adder more efficient and may slow it down. Thus, this article compares a conventional full adder with logic gates, a full adder with two 2:1 multiplexers, and a full adder with six 2:1 multiplexers in terms of power usage, time delay of the Sum and Carry outputs, and technology (0.6 μm).

The use of floating-point units (FPU) in digital signal processing has increased due to the range and the high precision numbers that can be represented. These units are required in image processing, digital filters with infinite impulse response (IIR), finite impulse response (FIR), and digital controllers, to obtain accurate results and avoid unstable responses, however, to implement them, some processors have built-in units, this implies a technological dependency of the manufacturers when prototypes are developed. To avoid such dependency, this article presents the design of modules for the most used operations in digital signal processing: multiplication and addition/subtraction. To be able to implement these operations in any Field Programmable Gate Array (FPGA), the steps and considerations to be aware of are presented, such as exceptions, rounding, and normalization of operands. Results are verified using the MODELSIM® test bench and the error rate was determined using MATLAB®. [ABSTRACT FROM AUTHOR]

This paper proposes a configurable reduced worst-case error approximate adder, named BEAD (B ounded E rror A pproximate A d der). The proposed adder is based on segmentation and carry speculation methods to cut long critical paths. Furthermore, a high accuracy speculation method is proposed to calculate the sum bits. However, the data of real-world applications is often not uniformly distributed, which leads to taking values that result in a worst-case error of the approximate adder quite frequently; therefore, considerable distortion occurs at the output. To overcome this, the carry prorogation scheme of the BEAD is such that the error distance is bounded to a given value, which makes it more accurate rather than prior works. Specifically, the BEAD offers a smaller worst-case error in addition to improved mean relative error distance. The results show between 50% and 80% smaller maximum error compared to the related works. Also, by synthesizing the different adders using a 15-nm FinFET technology, the results demonstrate that the BEAD has at least 30% area saving compared to the exact adder in the various studied configurations. The proposed adder achieves the almost lowest figure of cost (FoC) compared to state-of-the-art approximate adders. Moreover, BEAD's evaluation in image processing and DCT applications shows its great superiority over recently proposed structures. • Porposing an approximate adder based on segmentation and carry speculation methods. • Proposing a high precision speculation method to calculate the sum bits. • Bounding the error distance achieving in a smaller worst-case error. • Achieving the lowest figure of cost compared with prior approximate adders. [ABSTRACT FROM AUTHOR]

Many applications, such as integrated circuit based digital signal processors (DSPs) and arithmetic logical units (ALUs), rely on adders and subtractors, which are fundamental blocks. Traditional adders and subtractors were created using complementary metal oxide semi-conductor (CMOS) and field effect transistor (FET) technologies, which have increased the number of transistors, path delays, and power consumption. Therefore, this article focuses on the implementation of hybrid adders and subtractors utilizing FinFET and graphene nano-ribbon FET (GnrFET) based nanotechnologies. Initially, a multiplexer logic-based carry output predictable full adder (COPFA) is developed with a fast selection of carry-outputs, which significantly reduces the delays generated in sum estimation. Then, a path selectable reconfigurable hybrid adder (PSRHA) is developed by selecting the high-speed and low-speed carry propagation paths through the COPFA module. Further, a path selectable reconfigurable hybrid subtractor (PSRHS) also developed using two-complement PSRHA addition. Finally, a single architecture for both addition and subtraction are achieved through a joint reconfigurable hybrid adder and subtractor (JRHAS). From the simulations, the COPFA module resulted in a propagation delay (PD) of 7.2792 ns, static power consumption (SPC) of 2.4369nw, and total energy consumption (TEC) of 0.9077 nJ, while the PSRHA module resulted in PD of 2.45317 ns, SPC of 2.55681nw, TEC of 0.0912 nJ. In addition, the PSRHS module resulted in PD as 2.5297 ns, SPC as 2.8428nw, TEC as 0.0662 nJ, and the JRHAS module resulted in PD as 17.178 ns, SPC as 5.4036nw, TEC as 2.0543 nJ. Overall simulations revealed that the proposed COPFA, PSRHA, PSRHS, and JRHAS resulted in optimal performance as compared to conventional methods in terms of power, delay, and energy metrics. • MFA is developed with 10 transistors using MSLs. Then, COPFA is developed by changing the carry out operation of MFA. • Implementation of a 4-bit MRCA using MFA modules and developing 4-bit PSHA by introducing COPFA modules in MRCA. • In addition, a 4-bit PSHS is developed using two complementation addition properties with PSHA as building block. • Further, PSRHA and PSRHS are developed by introducing the reconfigurable properties in PSHA, and PSHS, respectively. • Finally, a unified architecture for both addition and subtraction operations are carried out using 4-bit JHAS and JRHAS modules. [ABSTRACT FROM AUTHOR]

Adders and Subtractors are an integral part of every digital information processing system. In general, it is always preferred to have a unified hardware that can perform both operations to reduce the area of circuits. The transistor technology is facing several difficulties to cope up with the targets set by Moore's law. Researchers have started to focus on finding alternatives. Quantum-dot Cellular Automata nanotechnology is suggested by the researchers for circuit design at nanoscale levels. A full adder-subtractor circuit using clock zone and multilayer crossover are proposed in this work. The results show that they have minimal cells and area. The fault tolerance capacity of the designs to missing cell defects is also analyzed. The full adder-subtractor coplanar design is 86.7% fault resistant and the multilayer design is 76.5% fault resistant. The coherence vector simulation engine is used to perform all the simulations in QCA designer. [ABSTRACT FROM AUTHOR]

The Very Large-Scale Integration (VLSI) industry is currently experiencing rapid growth in chip verification and design. This research focuses on generating a waveform, simulating, and verifying the Universal Verification Methodology (UVM) adder code using the QuestaSim tool and the UVM methodology. The functional verification community and researchers have an interest in UVM as it offers flexibility, reusability, and reliability properties that are useful for verifying complex chip systems. The main objective of this research is to verify the code of the UVM adder using the QuestaSim tool, which is a widely used tool for verifying digital circuits. Additionally, it aims to demonstrate the effectiveness of using the UVM methodology in verifying complex chip systems and highlights the importance of developing reliable and efficient verification methods for the VLSI industry. [ABSTRACT FROM AUTHOR]

The adder is a vital part of the Central Processing Unit (CPU) that can perform computational operations. It is used in digital components, mainly in the design of integrated circuits. Recent decades have seen a sharp rise in demand for mobile electronics, which has increased the need for highly efficient Very Large-Scale Integration (VLSI) structures. All operations must be computed using low-power, space-efficient designs that run faster. The Kogge-Stone adder (KSA) is an extension of the carry look-ahead adder which is used for performing fast addition in high-performance computing systems. This study compares the latency, space, and energy used by the Kogge-Stone Adder after development and implementation in Xilinx Vivado using Verilog to those of the Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA). The results show that the KSA has a decrease in power consumption as well as improvements in high speed and area compaction when compared to the RCA and CLA. [ABSTRACT FROM AUTHOR]