High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier.

Encryption algorithms work with very large key values to provide higher security. To process high-capacity data in real time, we need advanced hardware structures. Today, compared to previous design methods, hardware solutions can be designed more easily using Field-Programmable Gate Arrays (FPGAs). Over the past decade, FPGA speeds, capacities, and design tools have been improving. Thus, the hardware that can process high-capacity data can be designed and produced with lower costs. This study aims to create the components of a high-speed arithmetic unit that can process high-capacity data and be used for FPGA encoding algorithms. In this study, multiplication algorithms were analyzed. High-capacity adders that constitute high-speed multiplier and look-up tables were designed using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. Simulation results were obtained using the ModelSIM and ISIM programs. [ABSTRACT FROM AUTHOR]