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The room-temperature ferroelectricity of low-dimensional ferroelectric materials δ-SiX (X = S and Se) has been predicted and it could be tuned by applying a strain. Moreover, magnetism could be introduced in 1D-SiX nanowires by hole doping.

In this work, we present a four-transistor-two-resistor (4T2R) ternary content addressable memory (TCAM) bit cell based on the resistive memory (RRAM), comprising the conventional two-transistor-two-resistor (2T2R) cell with two additional comparison transistors. It can effectively amplify the match-line signal ratio (ML-ratio), lower the leakage current of the match cell ( ${I}_{{\mathrm {MATCH}}}$ ), and suppress the read disturbance. The proposed concept is silicon verified using the 180 nm CMOS technology with transition-metal-oxide (TMO) RRAM integrated at the back-end-of-line (BEOL). It achieves a considerable ML-ratio of 1860 and a low ${I}_{{\mathrm {MATCH}}}$ of 11.15 nA on average. In a typical search operation, it shows a negligible ML drop at the match case and a large ML swing range at the mismatch case. The SPICE simulation results further show it can support a long word-length (WDL) of 256 under a clock rate of 100 MHz for search operations, which demonstrates its promise for highly parallel nonvolatile TCAM.

Hopfield neural network, as a recurrent neural network, has been widely used to solve non-deterministic polynomial time-hard problems. However, the network tends to get trapped into local minima and thus converge to sub-optimal solutions. In this work, the intrinsic read noise in the memristive Hopfield network was harnessed as the random perturbation source to mitigate this problem. Firstly, the read noise in devices (TiN/TaO x /HfO x /TiN) at different resistance levels from a 1 Kb array was statistically measured, and the distribution of it was extracted. Then the effect of reading noise levels on the performance of a $64 \times 64$ network solver is quantitatively evaluated through confining all devices with the identical distribution. Based on such a strategy, the success probability, the distribution of distance, the energy consumption, and time to solution, at different noise levels and iteration cycles were investigated. The simulated results demonstrate that the intrinsic read noise in the resistive weight matrix is indeed helpful for the network to escape from local minima, serving as a useful computing resource.

3D Convolutional Neural Networks (CNNs) has been widely used for medical image analysis such as magnetic resonance imaging (MRI) and video recognition due to their intrinsic 3D characteristics. This letter presents 3D convolution operations realized by an 8-layers 3D vertical resistive random access memory (VRRAM) under a field-programmable gate array (FPGA)-controlled relay-matrix based test platform. As an implementation, 3D Prewitt operators are used for edge surface detection of 3D version MNIST handwritten digits with ${16}\times {16}\times {16}$ pixels. The experimental results show that 3D convolution kernels can be correctly implemented on our in-house 3D VRRAM with higher parallelism than the conventional architecture. Besides, the proposed 3D VRRAM meets the demands of low power and high capacity for 3D CNN accelerator, paving the way of 3D VRRAM-based processing-in-memory (PIM) architecture for 3D CNNs.

A memristor with a bilayer electrolyte structure (Pt/C/NbOx/TiN) is proposed as a self-rectification and quasi-linear electronic synapse. The device shows self-rectifying analogue memristive behavior with > 106 rectification ratio, which can solve the sneak current problem in crossbar array without additional hardware burden. Under identical pulses in potentiation process, the device conductance is quasi-linearly changed with 9.16% nonlinearity. In addition, the conductance change rate of device is effectively tuned by altering amplitudes and frequencies of spike pulses. Benefiting from the quasi-linear conductance change characteristics, excellent classification accuracy (95.7%) is achieved for the application of handwritten digit classification with a two-layer perceptron based on MINST stimulation.

The visual perception system is the most important system for human learning since it receives over 80% of the learning information from the outside world. With the exponential growth of artificial intelligence technology, there is a pressing need for high-energy and area-efficiency visual perception systems capable of processing efficiently the received natural information. Currently, memristors with their elaborate dynamics, excellent scalability, and information (ie.g.,/ivisual, pressure, sound,ietc./i) perception ability exhibit tremendous potential for the application of visual perception. Here, we propose a fully memristor-based artificial visual perception nervous system (AVPNS) which consists of a quantum-dot-based photoelectric memristor and a nanosheet-based threshold-switching (TS) memristor. We use a photoelectric and a TS memristor to implement the synapse and leaky integrate-and-fire (LIF) neuron functions, respectively. With the proposed AVPNS we successfully demonstrate the biological image perception, integration and fire, as well as the biosensitization process. Furthermore, the self-regulation process of a speed meeting control system in driverless automobiles can be accurately and conceptually emulated by this system. Our work shows that the functions of the biological visual nervous system may be systematically emulated by a memristor-based hardware system, thus expanding the spectrum of memristor applications in artificial intelligence.

A self-organizing map (SOM) is a powerful unsupervised learning neural network for analyzing high-dimensional data in various applications. However, hardware implementation of SOM is challenging because of the complexity in calculating the similarities and determining neighborhoods. We experimentally demonstrated a memristor-based SOM based on Ta/TaOx/Pt 1T1R chips for the first time, which has advantages in computing speed, throughput, and energy efficiency compared with the CMOS digital counterpart, by utilizing the topological structure of the array and physical laws for computing without complicated circuits. We employed additional rows in the crossbar arrays and identified the best matching units by directly calculating the similarities between the input vectors and the weight matrix in the hardware. Using the memristor-based SOM, we demonstrated data clustering, image processing and solved the traveling salesman problem with much-improved energy efficiency and computing throughput. The physical implementation of SOM in memristor crossbar arrays extends the capability of memristor-based neuromorphic computing systems in machine learning and artificial intelligence.

Biological neural networks are connected in a highly recurrent manner, which displays complex activity patterns spontaneously upon an awareness stimulus. Here, we emulate such a network based on a recurrently connected memristor array. To generate a target function, a first-order and controlled error (FORCE) learning rule that only needs to modify a small fraction of connections is introduced. This rule tries to minimize the amount of modification and thus is especially suitable for memristor-based synapses. After learning, the network could spontaneously generate the desired function after a random stimulus, just as the biological systems do.

In this work, a multi-functional self-rectifying memristor (Pt/TiO x /Ti) is fabricated. The device shows convertible volatile and non-volatile resistive switching. More importantly, the device has a high rectifying ratio in both switching modes (~105 for volatile and 106 for non-volatile), which is favorable for high-density 3D vertical integration. The convertible multi-switching behaviors and high self-rectifying ratio in a single memristor provide the flexibility for multi-functional applications in a large-scale array.

In this work, we demonstrate a flexible NbO x -based memristor for spiking neuron implementation. The NbO x , device exhibits stable threshold switching behavior and superior bending capability with a curvature radius of 2.5 mm. Based on such a device, we build a Leaky Integrate-and-Fire neuron and achieve four basic neuron features: all-or-nothing, threshold-driven spiking, refractory period, and strength-modulated frequency response. Moreover, the constructed flexible neuron is compatible with wearable sensing systems and can transform sensed analog signals to spike signals, leading them favorably to be used as neural interfaces.

Spiking neural network, inspired by the human brain, consisting of spiking neurons and plastic synapses, is a promising solution for highly efficient data processing in neuromorphic computing. Recently, memristor-based neurons and synapses are becoming intriguing candidates to build spiking neural networks in hardware, owing to the close resemblance between their device dynamics and the biological counterparts. However, the functionalities of memristor-based neurons are currently very limited, and a hardware demonstration of fully memristor-based spiking neural networks supporting in-situ learning is very challenging. Here, a hybrid spiking neuron combining a memristor with simple digital circuits is designed and implemented in hardware to enhance neuron functions. The hybrid neuron with memristive dynamics not only realizes the basic leaky integrate-and-fire neuron function but also enables the in-situ tuning of the connected synaptic weights. Finally, a fully hardware spiking neural network with the hybrid neurons and memristive synapses is experimentally demonstrated for the first time, and in-situ Hebbian learning is achieved with this network. This work opens up a way towards the implementation of spiking neurons, supporting in-situ learning for future neuromorphic computing systems.

In this article, we analyzed the experimental data based on the TaOx memristor and found that the threshold switching (TS) characteristics are related to temperature, and its logarithmic I–V curve is in good agreement with the space charge limiting current conduction mechanism. We use this mechanism to establish a TS physical model and then use the physical model to build an LTspice model. The model data are fitted with the experimental data, which is basically consistent. Next, using the TS memristor to simulate a leaky integrate-and-fire neuron circuit, the basic dynamics are realized. By changing the external temperature of the memristor, the output frequency of the neuron will be more intense as the temperature increases. Finally, an artificial spiking neural network (SNN) was built based on this neuron circuit for MNIST recognition task. In this SNN, the input signals fused both voltage amplitude and temperature to achieve neuromorphic multimodal preprocessing and enhance the recognition accuracy. These results demonstrated the reliability of the model, which enhanced the flexibility for exploring the application of TaOx-based TS memristors.

In this work, a compact model of the diffusive memristor is proposed from the perspective of the transition of electronic transmission mechanisms induced by the dynamics of the filament. First, a new physical model is established based on tunneling mechanisms that are used to fit the experimental data, and the results indicate that it is versatile enough for various diffusive memristors. In addition, the threshold voltage (V th) of the diffusive memristor negatively correlates with the ratio of ionic migration and the diffusion coefficient (u i /Ds), and the hold voltage (V h) positively correlates with the ratio of ionic diffusion and the migration coefficient (Ds/u i), which is useful for the selection of materials to achieve target electrical properties. Furthermore, the different parameters that influence the simulated switching curve are explored. The results indicate that the desired electrical characteristics can be obtained by adjusting these parameters. A compact electrical module model is then built and tested in LTspice to carry out bio-neuron and bio-synaptic performances completely. These simulations demonstrate that the model is reliable for exploring diffusive memristor applications.

In this work, we demonstrate that a Ta/TaO

SNNs with temporal coding (TC), inspired by the human visual system, have a powerful ability to enable fast and low-power neuromorphic computing. Memristive devices show excellent performance on emulating spiking neurons and synapses in hardware. However, the neuron circuits used for implementing a fully memristive TC SNN are absent. In this work, for the first time, we demonstrate a LIF neuron based on a NbO x device to meet the requirements for the hardware implementation of TC SNNs. The neuron fires at most one spike within an inference window, and its spiking latency inverse to the input current intensity. Using such a neuron, we further experimentally demonstrated a fully memristive TC SNN (256 × 5) to recognize the Olivetti face patterns. Attributing to the one-spike scheme, the TC SNN achieves a sparser spiking number (~ 72 × reductions), faster inference speed (> 1.5 × improvement), lower power (~ 53 × reductions) than what happens in rate-coding SNNs.

Spiking neural network, consisting of spiking neurons and plastic synapses, is a promising but relatively underdeveloped neural network for neuromorphic computing. Inspired by the human brain, it provides a unique solution for highly efficient data processing. Recently, memristor-based neurons and synapses are becoming intriguing candidates to build spiking neural networks in hardware, owing to the close resemblance between their device dynamics and the biological counterparts. However, the functionalities of memristor-based neurons are currently very limited, and a hardware demonstration of fully memristor-based spiking neural networks supporting in situ learning is very challenging. Here, a hybrid spiking neuron by combining the memristor with simple digital circuits is designed and implemented in hardware to enhance the neuron functions. The hybrid neuron with memristive dynamics not only realizes the basic leaky integrate-and-fire neuron function but also enables the in situ tuning of the connected synaptic weights. Finally, a fully hardware spiking neural network with the hybrid neurons and memristive synapses is experimentally demonstrated for the first time, with which in situ Hebbian learning is achieved. This work opens up a way towards the implementation of spiking neurons, supporting in situ learning for future neuromorphic computing systems.

In this work, by incorporating different electrodes (Ta/Ti) onto TaOx dielectric layer, we studied both the conductance reading and conductance updating (long term potentiation and depression) linearities in the two RRAM devices. Owing to the composition modulation (CM) mechanism, the Ta-electrode device shows better conductance reading and updating linearities. The RRAM device linearities directly influence the performance of the neural network when the devices are used as synapses. System evaluation of a two-layer neural network considering the conductance reading and updating linearity factors further confirm that both the training and inference accuracies of Ta electrode device are better than those of the Ti electrode one. We believe that this work could serve as a powerful reference for engineering synaptic devices with good linearity for neuromorphic computing applications.

Selector is important for emerging non-volatile memory arrays to settle the sneak path problem and inhibit the array leakage current. The turn-off current of the selector determines the ability of selector to inhibit the leakage current. Here, selector models with the structure of graphene/g-GaN/graphene show ultra-low turn-off current. First, combining the plane electrostatic potential and the current–voltage characteristic of switch layers of heterojunctions, it can be concluded that the resistance switching mechanism is based on Schottky barrier at the interface. Moreover, three selector models with different switch layers (model A, B, C) are explored to study the influence of the switch layer structure on the device. The plane average electrostatic potential of selectors shows that the different structures of the switch layer result in the difference of the threshold voltage (V th), owing to the different interface barrier. Finally, the electronic transmission shows each selector have an ultra-low turn-off current (I off) and high nonlinearity, which could better suppress the leakage current in array. This work supplies a potential implementation scheme for the selector with ultra-low turn-off current.

Resistive switching random access memory (RRAM) is considered as one of the potential candidates for next-generation memory. However, obtaining an RRAM device with comprehensively excellent performance, such as high retention and endurance, low variations, as well as CMOS compatibility, etc., is still an open question. In this work, we introduce an insert TaO x layer into HfO x -based RRAM to optimize the device performance. Attributing to robust filament formed in the TaO x layer by a forming operation, the local-field and thermal enhanced effect and interface modulation has been implemented simultaneously. Consequently, the RRAM device features large windows (> 103), fast switching speed (~ 10 ns), steady retention (> 72 h), high endurance (> 108 cycles), and excellent uniformity of both cycle-to-cycle and device-to-device. These results indicate that inserting the TaO x layer can significantly improve HfO x -based device performance, providing a constructive approach for the practical application of RRAM.

Neuromorphic computing based on spikes offers great potential in highly efficient computing paradigms. Recently, several hardware implementations of spiking neural networks based on traditional complementary metal-oxide semiconductor technology or memristors have been developed. However, an interface (called an afferent nerve in biology) with the environment, which converts the analog signal from sensors into spikes in spiking neural networks, is yet to be demonstrated. Here we propose and experimentally demonstrate an artificial spiking afferent nerve based on highly reliable NbOx Mott memristors for the first time. The spiking frequency of the afferent nerve is proportional to the stimuli intensity before encountering noxiously high stimuli, and then starts to reduce the spiking frequency at an inflection point. Using this afferent nerve, we further build a power-free spiking mechanoreceptor system with a passive piezoelectric device as the tactile sensor. The experimental results indicate that our afferent nerve is promising for constructing self-aware neurorobotics in the future., Though artificial sensory systems based on electronic devices have been realized, further transformation of data into spikes is required for neural network optimization. Here, based on NbOx Mott memristors, the authors report artificial spiking afferent nerves for accessing spiking systems and demonstrate spiking mechanoreceptor systems.

Resistive switching devices based on binary transition metal oxides have been widely investigated. However, these devices invariably manifest threshold switching characteristics when the active metal electrode is silver, the dielectric layer is hafnium oxide and platinum is used as the bottom electrode, and have a relatively low compliance current ( 108 and sub-threshold swing of ∼1 mV dec−1. After introducing a graphene interface barrier, high stress dependent (forming at +3 V) formation of localized conducting filaments embodies stable nonvolatile memory characteristics with low set/reset voltages (

The human memory system plays an indispensable role in oblivion, learning, and memorization. Implementing a memory system within electronic devices contributes an important step toward constructing a neuromorphic system that emulates advanced mental functions of the human brain. Given the complex time‐tailoring requirement, integrating a human memory system into one system is a great challenge. Here, one van der Waals heterostructure with flexible time‐tailoring ability is demonstrated, which can meet the high requirement of human memory system programming. By stacking volatile and nonvolatile function layers, all basic memory types, including sensory memory, short‐term and long‐term memory are integrated into the device and the transition between these memory types are flexible. Moreover, decision‐making action and in situ result storage are also demonstrated. It is anticipated that the demonstrated time‐tailoring system will support the model of a human memory system., van der Waals heterostructures with time‐tailoring ability are developed for human memory system programming. Retention time can be tailored from milliseconds to kiloseconds. Thus, a human memory system with rich functionalities is implemented in this cell and the system also has a capability of decision‐making and in situ data storage.