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136 results on '"Zhou, Xianda"'

3. IEA: Inner Ensemble Average within a convolutional neural network

Author

Mohamed, Abduallah, Hua, Xinrui, Zhou, Xianda, and Claudel, Christian

Subjects
Computer Science - Machine Learning, Statistics - Machine Learning
Abstract

Ensemble learning is a method of combining multiple trained models to improve model accuracy. We propose the usage of such methods, specifically ensemble average, inside Convolutional Neural Network (CNN) architectures by replacing the single convolutional layers with Inner Average Ensembles (IEA) of multiple convolutional layers. Empirical results on different benchmarking datasets show that CNN models using IEA outperform those with regular convolutional layers. A visual and a similarity score analysis of the features generated from IEA explains why it boosts the model performance., Comment: Updating results

Published
2018

5. MojiTalk: Generating Emotional Responses at Scale

Author

Zhou, Xianda and Wang, William Yang

Subjects
Computer Science - Computation and Language, Computer Science - Artificial Intelligence
Abstract

Generating emotional language is a key step towards building empathetic natural language processing agents. However, a major challenge for this line of research is the lack of large-scale labeled training data, and previous studies are limited to only small sets of human annotated sentiment labels. Additionally, explicitly controlling the emotion and sentiment of generated text is also difficult. In this paper, we take a more radical approach: we exploit the idea of leveraging Twitter data that are naturally labeled with emojis. More specifically, we collect a large corpus of Twitter conversations that include emojis in the response, and assume the emojis convey the underlying emotions of the sentence. We then introduce a reinforced conditional variational encoder approach to train a deep generative model on these conversations, which allows us to use emojis to control the emotion of the generated text. Experimentally, we show in our quantitative and qualitative analyses that the proposed models can successfully generate high-quality abstractive conversation responses in accordance with designated emotions.

Published
2017

9. Potential of the Amorphous Oxide Semiconductors for Heterogeneous Power Integration Applications

Author

Zhou, Xianda, Lu, Lei, Liu, Yang, Wang, Kai, Guo, Yufeng, Ma, Hanbin, Yu, Jun, Nathan, Arokia, Sin, Johnny Kin On, Zhou, Xianda, Lu, Lei, Liu, Yang, Wang, Kai, Guo, Yufeng, Ma, Hanbin, Yu, Jun, Nathan, Arokia, and Sin, Johnny Kin On

Abstract

In the emerging heterogeneous power integration applications, the power devices have to be fabricated on metal/glass/organics. In this field, amorphous oxide semiconductors (AOSs) have being the dominant semiconductor material to fulfill the low-temperature fabrication requirement. In the AOSs, the theoretical tradeoff between specific oN-resistance (R-O(N, )sp) and breakdown voltage (BV) is discussed. It is found that the tradeoff is rather different from the situation in these commonly used single-crystal semiconductors. In the AOSs, under the one-dimensional condition, R-ON(, sp) is not proportional to BV2 due to the unique charge carrier mobility dependence on the carrier concentration. An analytical model has been extracted to describe such dependence, and it is found that R-O(N, sp) is proportional to BV4. Moreover, it is revealed that under a two-dimensional condition, such as reduced surface field (RESURF) condition, a "heavily doped" drift region can be used, and the mobility degradation issue could be resolved.

Published
2023

14. C-RISE: A Post-Hoc Interpretation Method of Black-Box Models for SAR ATR.

Author

Zhu, Mingzhe, Cheng, Jie, Lei, Tao, Feng, Zhenpeng, Zhou, Xianda, Liu, Yuanjing, and Chen, Zhihan

Subjects
SYNTHETIC aperture radar, AUTOMATIC target recognition, RADAR signal processing, CONVOLUTIONAL neural networks, RADAR targets, SPACE-based radar, SUCCESSIVE approximation analog-to-digital converters, GAUSSIAN processes
Abstract

The integration of deep learning methods, especially Convolutional Neural Networks (CNN), and Synthetic Aperture Radar Automatic Target Recognition (SAR ATR) has been widely deployed in the field of radar signal processing. Nevertheless, these methods are frequently regarded as black-box models due to the limited visual interpretation of their internal feature representation and parameter organization. In this paper, we propose an innovative approach named C-RISE, which builds upon the RISE algorithm to provide a post-hoc interpretation technique for black-box models used in SAR Images Target Recognition. C-RISE generates saliency maps that effectively visualize the significance of each pixel. Our algorithm outperforms RISE by clustering masks that capture similar fusion features into distinct groups, enabling more appropriate weight distribution and increased focus on the target area. Furthermore, we employ Gaussian blur to process the masked area, preserving the original image structure with optimal consistency and integrity. C-RISE has been extensively evaluated through experiments, and the results demonstrate superior performance over other interpretation methods based on perturbation when applied to neural networks for SAR image target recognition. Furthermore, our approach is highly robust and transferable compared to other interpretable algorithms, including white-box methods. [ABSTRACT FROM AUTHOR]

Published
2023
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22. Reliable High-Performance Amorphous InGaZnO Schottky Barrier Diodes with Silicon Dioxide Passivation Layer

Author

Zhou, Jitong, Wang, Yunping, Zhou, Xianda, Li, Guijin, Xia, Zhihe, Yeung, Fion Sze Yan, Wong, Man, Kwok, Hoi Sing, Zhang, Shengdong, Lu, Lei, Zhou, Jitong, Wang, Yunping, Zhou, Xianda, Li, Guijin, Xia, Zhihe, Yeung, Fion Sze Yan, Wong, Man, Kwok, Hoi Sing, Zhang, Shengdong, and Lu, Lei

Abstract

Sputtered amorphous indium-gallium-zinc -oxide (a-IGZO) Schottky barrier diodes (SBDs) were comparatively investigated without and with a passivation layer (PL). The a-IGZO SBDs without PLs were found to be highly unstable in the atmosphere and under electrical stress. During the implementation of silicon dioxide (SiO2) PL, the associated thermal oxidization and hydrogen doping resulted in high-performance metrics, including an ideality factor close to the unity, a high Schottky barrier of 0.82 eV, and a large current rectification ratio of over 108. Benefited from the PL protection and ideal Schottky contact, the environmental and electrical stabilities of SBDs were significantly enhanced.

Published
2021

34. Superjunction MOSFET With Dual Built-In Schottky Diodes for Fast Reverse Recovery: A Numerical Simulation Study

Author

Wei, Jin ECE, Zhang, Meng, Jiang, Huaping, Zhou, Xianda, Li, Baikui, Chen, Jing, Wei, Jin ECE, Zhang, Meng, Jiang, Huaping, Zhou, Xianda, Li, Baikui, and Chen, Jing

Abstract

A new superjunction MOSFET (SJ-MOSFET) architecture with dual built-in Schottky diodes is proposed and studied with the numerical TCAD simulations.This letter is based on silicon. One Schottky contact is formed at the top of the n-pillar, while the other is formed at the bottom of the p-pillar. During the reverse conduction period, the Schottky junctions turn on at a lower voltage than the PN junction. The current flows through n-pillar and p-pillar in parallel, so the potential difference across the PN junction is kept below its turn-on voltage. Thus, minority carrier injection through the PN junction is completely suppressed, leading to a superior reverse recovery performance. Integration of a single Schottky contact to either the n-pillar or the p-pillar cannot completely suppress the turn-on of the PN junction in the SJ-MOSFET due to the potential drop created by the current through only one type of the pillars. Furthermore, the proposed dual-Schottky SJ-MOSFET reduces the gate charge (Q G ) and the gate-to-drain charge (Q GD ), compared with the conventional SJ-MOSFET, leading to better figures of merit.

Published
2019

35. Superjunction MOSFET With Dual Built-In Schottky Diodes for Fast Reverse Recovery: A Numerical Simulation Study

Author

Wei, Jin, Zhang, Meng, Jiang, Huaping, Zhou, Xianda, Li, Baikui, Chen, Kevin Jing, Wei, Jin, Zhang, Meng, Jiang, Huaping, Zhou, Xianda, Li, Baikui, and Chen, Kevin Jing

Abstract

A new superjunction MOSFET (SJ-MOSFET) architecture with dual built-in Schottky diodes is proposed and studied with the numerical TCAD simulations.This letter is based on silicon. One Schottky contact is formed at the top of the n-pillar, while the other is formed at the bottom of the p-pillar. During the reverse conduction period, the Schottky junctions turn on at a lower voltage than the PN junction. The current flows through n-pillar and p-pillar in parallel, so the potential difference across the PN junction is kept below its turn-on voltage. Thus, minority carrier injection through the PN junction is completely suppressed, leading to a superior reverse recovery performance. Integration of a single Schottky contact to either the n-pillar or the p-pillar cannot completely suppress the turn-on of the PN junction in the SJ-MOSFET due to the potential drop created by the current through only one type of the pillars. Furthermore, the proposed dual-Schottky SJ-MOSFET reduces the gate charge (Q G ) and the gate-to-drain charge (Q GD ), compared with the conventional SJ-MOSFET, leading to better figures of merit.

Published
2019

36. Fabrication and Characterization of High-Voltage NiO/β-Ga 2 O 3 Heterojunction Power Diodes.

Author

Luo, Haoxun, Zhou, Xianda, Chen, Zimin, Pei, Yanli, Lu, Xing, and Wang, Gang

Subjects
*HETEROJUNCTIONS, *DIODES, *P-N heterojunctions, *BREAKDOWN voltage, *THIN films, *NICKEL oxide, *NICKEL oxides
Abstract

This work presents the fabrication and characterization of a high-performance vertical Nickel oxide (NiO)/Beta gallium oxide ($\beta $ -Ga2O3) heterojunction p-n diode. The heterojunction was fabricated by sputtering a p-NiO thin film onto an epitaxial ${n}^{-}$ - $\beta $ -Ga2O3 drift layer. The sputtered NiO, revealed to be polycrystalline, showed an improved crystallinity after annealed in an oxygen ambient, while a seamless contact with the underneath single crystalline $\beta $ -Ga2O3 was observed. A high hole concentration of 1– $3\times 10^{{19}}$ cm−3 and an improved Ohmic contact were also obtained by the annealing process, as confirmed by the Hall and TLM measurements, respectively. A high breakdown voltage (${V}_{\text {B}}$) of 1.4 kV and a low specific ON-resistance (${R}_{\text {on,sp}}$) of 2.7 $\text{m}\Omega \cdot $ cm2 were simultaneously achieved for the fabricated diodes, yielding a superior Baliga’s figure-of-merit (BFoM) of 0.73 GW/cm2. From the temperature-dependent current–voltage (${I}$ – ${V}$) measurements, two carrier transport mechanisms, namely interface recombination and multistep tunneling, have been identified in the forward conduction of the NiO/ $\beta $ -Ga2O3 heterojunction. The fast recovery property of the device, which was revealed by a double-pulse test, further confirmed the purposed carrier transport mechanisms. [ABSTRACT FROM AUTHOR]

Published
2021
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43. A Novel 700 V Monolithically Integrated Si-GaN Cascoded Field Effect Transistor

Author

Ren, Jie ECE, Tang, chak wah, Hao, feng, Jiang, Huaxing, Yang, Wentao, Zhou, xianda, Lau, Kei May, Sin, Johnny Kin On, Ren, Jie ECE, Tang, chak wah, Hao, feng, Jiang, Huaxing, Yang, Wentao, Zhou, xianda, Lau, Kei May, and Sin, Johnny Kin On

Abstract

In this letter, a novel monolithically integrated Si-GaN cascoded FET is designed and experimentally demonstrated for high-voltage power switching applications. The device is formed by monolithically connecting a low-voltage Si MOSFET and a high-voltage normally-on GaN MIS-HEMT on the same substrate in the cascode configuration. The interconnection distance is 50 μm which is only 2.5% of that of the conventional two-chip co-package approach (~2 mm). The fabricated cascoded FET features normally-off functionalities with a threshold voltage of 3.2 V, a drive current of 1850 A/cm2 (630 mA/mm) at the gate bias of 15 V, a gate swing of 20 V, a specific on-resistance of 3.3mΩ⋅cm2 and a breakdown voltage of 696 V.

Published
2018

44. Highly Sensitive a-Si:H PIN Photodiode Gated LTPS TFT for Optical In-Display Fingerprint Identification

Author

Zhou, Xianda ECE, Zhang, Meng, Xu, Yitong, Zhou, Wei, Wang, Kai, Nathan, Arokia, Wong, Man, Kwok, Hoi Sing, Zhou, Xianda ECE, Zhang, Meng, Xu, Yitong, Zhou, Wei, Wang, Kai, Nathan, Arokia, Wong, Man, and Kwok, Hoi Sing

Abstract

A hybrid optical sensor that is merged with the display driving, low‐temperature polysilicon thin‐film transistor (TFT) is reported. The sensor achieves a fill factor >70% and a photoconductive gain > 103%, which provides a promising solution for in‐display fingerprint identification.

Published
2018

45. Vertical ITO/SiOX/a-Si:H Photodiode-Gated Low-Temperature Polycrystalline Silicon Thin-Film Transistor Intended for In-Display Fingerprint Imaging Applications

Author

Zhou, Xianda, Zhang, Meng, Xu, Yitong, Wang, Kai, Wong, Man, Kwok, Hoi Sing, Zhou, Xianda, Zhang, Meng, Xu, Yitong, Wang, Kai, Wong, Man, and Kwok, Hoi Sing

Abstract

To embed an active pixel optical sensor in a display pixel for fingerprint imaging, an area-efficient and vertical ITO/SiOX/a-Si:H photodiode-gated low-temperature polycrystalline silicon dual-gate thin-film transistor with controllable photosensitivity is proposed and experimentally demonstrated. The device can be operated as a driving switch to the display pixel, and the driving current is insensitive to normal ambient light; the device can also be operated as an optical sensor, which provides 8 bits of effective data and reasonable detectable intensity range. The compact structure and dual-mode operation make it a promising solution to in-display, large-area fingerprint identification for smartphones.

Published
2018

46. A One-Transistor Active Pixel Sensor Formed by A Vertical Photodiode-Gated Low-Temperature Polysilicon Thin-Film Transistor

Author

Wang, Kai, Zhou, Xianda, Zhang, Meng, Xu, Yitong, Wong, Man, Kwok, Hoi Sing, Wang, Kai, Zhou, Xianda, Zhang, Meng, Xu, Yitong, Wong, Man, and Kwok, Hoi Sing

Abstract

We report a compact hybrid optical sensor by vertically integrating an a-Si:H photodiode and a low-temperature polysilicon (LTPS) thin-film transistor (TFT). Such a photodiode-gated LTPS TFT combines sensing, storage, and readout switch functions and also has an internal photoconductive gain, resulting in a one-transistor active pixel sensor intended for high-resolution and high-sensitivity large-area imaging. © 2018 IEEE.

Published
2018

47. Highly Sensitive a-Si:H PIN Photodiode Gated LTPS TFT for Optical In-Display Fingerprint Identification

Author

Zhou, Xianda, Zhang, Meng, Xu, Yitong, Zhou, Wei, Wang, Kai, Nathan, Arokia, Wong, Man, Kwok, Hoi Sing, Zhou, Xianda, Zhang, Meng, Xu, Yitong, Zhou, Wei, Wang, Kai, Nathan, Arokia, Wong, Man, and Kwok, Hoi Sing

Abstract

A hybrid optical sensor that is merged with the display driving, low‐temperature polysilicon thin‐film transistor (TFT) is reported. The sensor achieves a fill factor >70% and a photoconductive gain > 103%, which provides a promising solution for in‐display fingerprint identification.

Published
2018

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