Search

Desire to integrate electronic devices more closely into the everyday life of the consumer led to the emergence of flexible devices, which can conform to any shape surface. These flexible devices are lighter, thinner, and more resilient than their rigid counterparts. Since consumers these days are heavily concerned about the visual look of any product along with its technological features, the flexible devices also pave the way for innovation and creativity from the aesthetic point of view. As more and more electronics including wearable devices and displays are shifting towards the flexible regime, their basic components like sensors and integrated circuits are also required to be flexible and conformal. This paper reviews the development and evolution of several types of flexible MEMS sensors, accelerometers, and energy harvesters from the design, fabrication, and performance perspective.

We investigated the effect of channel hot carrier (CHC) stressing on the creation of gate oxide defect centers causing random telegraph signals (RTSs) in pMOSFETs. To identify these stress-induced hole traps in the oxide and fully characterize their trapping properties, variable temperature RTS measurements were performed from room temperature down to 215 K and repeated after each stressing interval, up to 1200 s. The trapping properties of the stress-induced defect sites and those present before stress are quantified, including the hole capture and emission activation energies, structural relaxation in the oxide network due to trapping/detrapping, and entropy change as well as the energy level and position of the trap in the oxide. Based on this information, disassociated III-Si and hydrogen bridge defects are identified as the hole trapping centers in SiO2. Difference was observed between the process- and stress-induced traps in the entropy change upon hole emission from the oxide trap to Si channel (electron capture from the Si valence band), implying the possibility of stress-induced structural defects being different than the native ones.

Although it is the worst degradation mechanism, the effect of channel hot carrier (CHC) stressing on random telegraph signals (RTS) has not been given enough attention in pMOSFETs. We report on the effect of CHC stressing on different RTS trap parameters namely screened scattering coefficient which controls the amount of charge carrier mobility fluctuations due to remote Coulomb scattering by the trap, RTS fluctuation amplitude, average capture time and capture cross-section. The generation of positive fixed oxide charge with stressing influences the screened Coulomb scattering of the channel carriers and therefore their mobility, in addition to the commonly accepted self-screening of the channel carriers. The two-dimensional mobility fluctuations model is adopted for analyzing the CHC effect on pMOSFETs. The comparison between theoretically and experimentally obtained screened scattering coefficients points toward the impact of the newly generated positive fixed oxide charge due to stressing. The decrease of the screened scattering coefficient results in increased RTS amplitude and decreased contribution of mobility fluctuations to RTS amplitude. Capture time and capture cross-section also change as the capture cross-section pre-factor has been impacted by the reduction of relaxation energy with stressing.

In recent years, material printing on flexible and disposable substrates has received substantial interest for realizing low cost electronic and sensing systems on large-areas. As a result, new methods such as printing and additive manufacturing, etc. have received significant attention to develop a wide range of easily deployable systems such as displays, sensors, and RFID smart tags. The technologies developed for silicon-based planar electronics and solid-state sensors is also being repurposed to meet the demands in the emerging field of flexible and printed sensors. This trend will continue as all market indicators point towards significant growth in this area. The exponential growth in flexible, printed and disposable sensor technology, the development of novel printable and solution processable nanomaterials, and the development of novel printing techniques have brought about a new wave of novel printed sensor technologies and applications. Considering this growth, it became necessary to provide a forum to discuss latest developments in the field and to bring together academia and industry to lay the future roadmap. The IEEE International Conference on Flexible and Printable Sensors and Systems (IEEE FLEPS) aims to be such a forum. The 2019 conference was the first edition, started by IEEE Sensors Council, with an aim to be a premier conference in the world. The high standards of the conference will be ensured by the steering committee and the track chairs formed by world-leading experts in the field.

We report on the investigation of random telegraph signals (RTSs) in pMOSFETs at variable temperatures to identify and characterize the hole traps residing at the oxide–semiconductor interface. Attractive center defects as well as a repulsive center defect are identified with trap location, capture cross section, remote Coulomb scattering coefficient, capture barrier energy, trap binding enthalpy, relaxation energy, and change in entropy with hole emission. The attractive centers responsible for RTS were a pair of dissociated three-coordinated silicon (D-III-Si) defects while the repulsive center was identified as a puckered/back-projected oxygen vacancy defect, [a pair of under-coordinated silicon (III-Si) and over-coordinated oxygen (III-O) defects]. Both contain ${E}\gamma ^{\prime }$ centers. This is the first time when such detailed analysis is reported on the hole traps in SiO2 which are responsible for RTS.

A complete investigation of the effect of Li doping on the physical, material, electromechanical and piezoelectric properties of ZnO nanowires (NWs) is presented. Low temperature hydrothermal growth technique is used to grow vertically aligned crystalline ZnO NWs doped with different concentrations of Li. Characterization techniques reveal considerable physical, material and electromechanical property modifications of the ZnO NWs due to the incorporation of Li dopants. Atomic Force Microscope is utilized to apply controlled amount of force on the fabricated NWs to assess their piezoelectric response. More than twenty two-fold improvement is observed in sensitivity due to the combined effect of modifications in NW geometry and piezoelectric properties with the addition of Li. Finite element method simulations were performed to decouple the individual effect of Li doping on the NW size and on the piezoelectric coefficient and to see how much each effect plays a role in the sensitivity improvement. It is estimated that the changes in the material and electromechanical properties alone are responsible for more than seven-fold improvement in the sensitivity. The impact of ‘kick-out’ diffusion mechanism of Li in ZnO is one of the major factors responsible behind this sensitivity improvement. It is also observed that there is an optimum level of Li doping concentration which can lead to the best piezoelectric performance by the ZnO NWs. The novelty of this work lies on the detailed analyses to illustrate the physics and impact of Li dopants in ZnO NW structures from a piezoelectric point of view towards improving their application as a nano-sensing and nano-energy harvesting element.

This paper presents a wafer-level vacuum-packaged z-axis capacitive micro accelerometer fabricated on a flexible polyimide substrate and encapsulated by another polyimide superstrate enabling the flexibility, bendability, and portability of both the device and the package. The novel low-cost and low-temperature encapsulation procedure requires a fewer fabrication steps than the processes, where a thin epitaxial Si layer or a full Si wafer with cavity is used as a superstrate. It also provides a better pliability. The fabricated micro accelerometers demonstrated excellent integrity when bowed down to 2-cm radius of curvature with the sensitivity varying between 139 and 174 fF/g, depending on the design, under the application of ±4 g of acceleration. The resonant frequencies varied from 800 Hz for the largest device to 1050 Hz for the smallest device. The results reported here represent the best performing, wafer-level-packaged flexible micro accelerometers to date.

Surface micro-machined z-axis capacitive accelerometers were designed and fabricated on a flexible polyimide substrate, conformal down to 2 cm radius of curvature with the stresses sustained by all layers well below the yield strength for each material. A novel UV-LIGA fabrication technique was developed to realize a thicker proof-mass (8 μm) compared to the spring (3 μm), thus decoupling the two important parameters: the stiffness and the proof-mass to achieve higher sensitivity. Devices with three different sizes were fabricated with the capability of sustaining under distinct amount of acceleration and tuned to frequencies ranging from 600 Hz to 1100 Hz. The largest device, having the area of 960 μm × 960 μm, showed a sensitivity of 187 fF/g with a SNR (Signal to Noise Ratio) of at least 100 when characterized at its resonance frequency of 800 Hz. The applied acceleration was ±4 g in addition to gravitation.

Random telegraph signals (RTS) have been used as a technique for gate oxide defect analyses for the last few decades. The time required by a gate oxide defect to capture and emit an inversion layer carrier can be used to extract the defect energy parameters. The RTS behavior measured at different temperatures can provide sufficient information to determine the structure and physical nature of the responsible defects. In addition, an RTS simulation tool is developed that can successfully reconstruct the RTS traces based on the trap parameters related to the defects. Application of electrical stress results in additional RTS in the output signal, which is believed to be the result of Si–Si bond breakage and creation of hole traps, or reactivation of passivated traps. Stressing the MOSFETs has also resulted in random activation and deactivation of oxide traps. This chapter focuses on the theoretical background of RTS in MOSFETs, sample setup for RTS measurements, data analyses, advantages, and limitations of using RTS to characterize defects.

This chapter provides a brief background to the development of multifunctional sensors that can conform to any surface. The objective is to achieve what is now referred to, as “Smart Skin” (sensitive skin as defined by Vladimir Lumelsky, one of its pioneers) is a large area, flexible array of sensors with data processing capabilities. The microsensors are integrated to give the capability of sensing several stimuli, mimicking a real skin, including but not limited to temperature, touch, and flow. Other requirements are flexibility and ability to stretch and wrinkle without any degradation in its sensing figures of merit. Additional capabilities can be incorporated such as biochemical sensing and decision-making, and energy harvesting. When incorporated with thin film transistors fabricated on flexible plastic substrates, a complete “Smart Skin” is achieved.

A MEMS wideband energy harvesting array design using linear and nonlinear generators is reported in this paper. An array comprising of four electrostatic energy harvesters using linear, softening, hardening springs and mechanical stoppers connected in parallel can work over a wide frequency range. Novel nonlinear spring design produces spring softening and hardening behaviors. Mechanical stoppers further enhance the operating frequency range of the hardening spring energy harvester. Mathematical model of the electromechanical system is derived and optimized using MATLAB. The system is built using Coventorware/MEMS+®. Simulation results indicated a maximum normalized power density of 1.97 µWs4/cm3-m2 is achieved over 600 Hz-1350 Hz frequency range. Moreover, following the method developed in this work, the device size is reduced by 89% compared to traditional array design technique.

An array of four out-of-plane, gap-closing, electret-based electrostatic energy harvesters capable to harvest over a wide frequency range is designed. The novel design consists of energy harvesters with linear springs, softening springs, hardening springs and mechanical stoppers. This unique method of designing array with combination of linear and nonlinear generators allows the system to harvest significant amount of power even with shift in vibration frequency. A dynamic model of the system is derived and optimized using MATLAB. The optimized system is built using Coventorware / MEMS+®. A maximum power of 75 nW is obtained over a frequency range of 450-760 Hz. The design also takes 75% less volume compared to an array of linear energy harvesters to generate over the same frequency range.

A novel optimized design of a triboelectric vibrational energy harvester having small MEMS scale size and low mass is presented in this work. The triboelectric energy harvester is designed to harvest energy from high frequency mechanical vibrations of machineries such as the skin of an aircraft. The novelty of this work lies in the integrated design and modeling of the energy harvester which enables it to be fabricated and packaged as a MEMS device in a traditional cleanroom environment. Dynamic optimization has been implemented on its geometric model to maximize the output power and power density. Simulation shows that at an acceleration magnitude of 9.8 ms-2 and operating frequency of 800 Hz, the device can generate an average power of 196.91 nW with surface and volume power densities of 13.1 mWm-2 and 1544.4 Wm-3, respectively. Due to its small size, low mass and comparatively high power density, this triboelectric energy harvester can have a significant impact in expanding the applications of the nano-sensors in wireless sensor nodes, in automobile industry, in space exploration programs, in micro- robotics and in prosthetics.

Uncooled infrared detectors (IR) on a polyimide substrate have been demonstrated where amorphous silicon (a-Si) was used as the thermometer material. New concepts in uncooled microbolometers were implemented during the design and fabrication, such as the integration of a germanium long-pass optical filter with the device-level vacuum package and a double layer absorber structure. Polyimide was used for this preliminary work towards vacuum-packaged flexible microbolometers. The detectors were fabricated utilizing a carrier wafer and low adhesion strength release layer to hold the flexible polyimide substrate during fabrication in order to increase the release yield. The IR detectors showed a maximum detectivity of 4.54 × 106 cm Hz1/2/W at a 4 Hz chopper frequency and a minimum noise equivalent power (NEP) of 7.72 × 10−10 W/Hz1/2 at a biasing power of 5.71 pW measured over the infrared wavelength range of 8–14 μm for a 35 μm × 35 μm detector. These values are comparable to other flexible microbolometers with device-level vacuum packaging which are found in literature.

The design, fabrication, performance simulation and characterization of a piezoelectric zinc oxide (ZnO) nanowire (NW) micro-energy harvester integrated with a microelectromechanical proof-mass/spring system are presented. Low temperature hydrothermal growth of vertically aligned nanowires together with MEMS surface micromachining and UV-LIGA (Lithographie, Galvanoformung, Abformung) processes were utilized to achieve efficient coupling of environmental vibrations to the nano energy harvester. The NWs were connected in series through the membrane/proof-mass structure to achieve higher output voltage. A novel polyimide fill-in and etch-back technique was employed to embed the NW tips into the membrane, such that the NWs were compressed and stretched by the membrane/proof-mass structure in response to the external vibrations. Peak power of 70 pW was observed across an optimal 7 MΩ load when the nano energy harvester was excited with an acceleration of 1.4 g at 40 Hz, corresponding to 22 mW/cm 3 volume-normalized power output. The measured voltage between the top and the bottom electrode was 21.4 mV for this case. The output frequency spectral density with 40 Hz excitation and output voltage with varying excitation frequency are also discussed.

Investigating random telegraph signals (RTS) observed in MOS devices is important for studying the gate-oxide defect characteristics and developing simulation and modeling tools in highly scaled devices. In this paper, we are presenting a comprehensive, variable-temperature, single-to-multitrap scalable RTS model and a simulation tool (RTSSIM) based on the first principles, and supported by experimental data. The physical and electrical characteristics of the actual oxide defects are considered, such as trapping barrier energy, capture cross section, trap-binding enthalpy, entropy change with emission, Coulombic scattering effect, and the trap location. Experimentally obtained time-domain switching data and RTS traces reconstructed by the developed simulation tool are compared for assessing the accuracy of the modeling. In this paper, we identified the trap species responsible for the RTS as an unrelaxed neutral oxygen deficiency center ( $V^{0}$ ODC II) with measured and theoretically verified relaxation energy of 1.11, 1.25, and 0.60 eV. RTSSIM is a tool used to mimic or reproduce a given noise measurement on a particular device. The simulation tool shows over 92% accuracy in replicating the RTS and trap characteristics. The model also represents the first realistic simulation of multilevel RTS.

A novel triboelectric energy harvesting (TEH) and sensing system scaled down to microelectromechanical systems (MEMS) size is presented. The design is structurally optimized for harvesting the highest average power and power density while ensuring the structural robustness. Unlike traditional triboelectric energy harvesters, this design results in a high operating frequency with a wide bandwidth. Adoption of MEMS fabrication techniques including the use of spin-coated Teflon AF rather than a Teflon sheet, adaptation of UV-LIGA (Ultra-Violet Lithographie, Galvanoformung, Abformung) with modifications and implementation of a thick polyimide sacrificial layer make the fabrication process unique. If excited by ±9.33 g external vibration with a frequency of 1.15 kHz, the TEH can generate 0.179 μW average power and 0.597 μW peak power at an optimum resistive load of 256 kΩ. The peak surface power density, volumetric power density and acceleration-normalized volumetric power density reach 3.98 μWcm−2, 2.64 mWcm-3 and 30.3 μWcm-3/g2, respectively. While the surface power density of the presented TEH is moderate, the volumetric power density and acceleration-normalized volumetric power density are quite competitive among the state-of-the-art designs. The TEH also demonstrates a wide operating frequency bandwidth of 920 Hz. If operated as an accelerometer, the device shows a linear sensitivity of 43 mV/g. Although the simulation predicts the optimum operating frequency and load resistance of the system to be at 800 Hz and 10 MΩ, respectively, the experimental results demonstrate these values to be at 1150 Hz and 256 KΩ. A few fabrication anomalies, most notably the notching in the Teflon layer and bowing of the proof-mass, are responsible for this deviation. In addition, a distortion is observed in the simulated output voltage profile which is not present in the experimental output voltage profile due to the presence of the parasitic capacitance in the experimental circuit. The aforementioned triboelectric energy harvester can have specific applications in the sensor and actuator systems in the aircraft industry as well as in the automobile industry, micro-robotic systems, prosthetic systems, and sensor nodes in the internet of things (IoT) due to its operating frequency and bandwidth range.

The effect of channel hot carrier stress has been investigated in pMOSFETs with respect to channel hole trapping by the gate oxide traps and the resultant Random Telegraph Signals (RTS) observed at the output. Process- and stress- induced oxide traps have been identified through RTS measurements. These traps are believed to be E′ centers, acting as hole-attractive or repulsive centers, causing RTS through correlated carrier number and mobility fluctuations. Generation of E′ centers as well as activation of the passivated oxide defects as a result of stress are thought to be the reasons behind observing the stress-induced RTS. Two of the observed defects: one process-induced and one stress-induced trap have disappeared and reappeared randomly with stress. We report the reaction of the defects with hydrogen to be responsible for the volatile nature of the traps. Hydrogen is either bound to the Si/SiO2 interface or trapped at the oxide defects. Applying the stress releases these hydrogen species, which then drift towards the gate through the oxide layer and react with the oxide defects to passivate them. Reaction with another hydrogen de-passivates the defect releasing H2. This is the first article that reports hydrogen to deactivate and reactivate oxide traps responsible for RTS.

The fabrication and characterization of micromachined piezoresistive absolute pressure sensors in a flexible substrate is presented. A suspended aluminum oxide diaphragm containing nichrome (Ni-80%/Cr-20%) piezoresistive sensors backed by a vacuum cavity was utilized to form the sensor. The piezoresistors were placed in a half-Wheatstone bridge geometry to provide a linear response and thermal stability. The average value of the gauge factor of nichrome was measured to be 1.95. The average normalized Hooge coefficient $\text{K}_{1/f}$ was found to be $4.64\times 10^{-11}$ for the nichrome piezoresistors. The pressure sensors displayed an average sensitivity of 1.25 nV/Pa and average value of noise equivalent pressure (NEPr) of 7.44 kPa in the bandwidth of 1–10 Hz in the 1/ $f$ -noise limited regime. In the Johnson noise-limited regime, the NEPr was found to be 10 Pa in a 1-Hz bandwidth. [2014-0028]

The physical origin of majority charge carrier fluctuations in the SiO2 interface of Si at accumulation has been investigated and analyzed for differently processed and voltage-rated reduced surface field (RESURF), lateral-double-diffused MOS (LDMOS) transistors. Surface carrier mobility fluctuation due to remote Coulomb scattering by the trapped charge in the gate oxide is identified as the dominant physical mechanism for LDMOS 1/f noise irrespective of process technologies. A significant contribution to the measured noise has been noted from the surface majority carrier mobility fluctuation due to trapped charge at the accumulation region of the extended drain region, dominant over other sources including the surface minority charge carrier fluctuations in the channel. Active oxide trap density was characterized spatially and for the first time up to ∼0.4 eV above the conduction band-edge of Si. The interface trap density in the unstressed devices (∼8 × 106 cm−2) increased more than an order of magnitude (∼1 × 108 cm−2) after the devices were stressed for 10,000 sec at their individual worst drain current and on-resistance degradation conditions. The extracted Si/SiO2 interface trap density above the silicon conduction band edge was found to be several orders of magnitude lower than that reported for silicon mid-gap energies, even after stressing. Since the traps near the quasi-Fermi level for electrons are active in trapping–detrapping, and the Fermi level is energetically positioned above the conduction band edge of Si in the investigated devices as compared to the previously reported observations, the lower trap density obtained here is an indication for reversal of the well-known exponential trap energy distribution beyond the conduction band-edge of Si. These findings shift the focus from the channel to the gate overlap section of the extended drain and the quality of the Si/SiO2 interface in that region.

Flexible, bendable tactile pressure sensors are developed with crystalline ZnO nanorods as a robotic skin or as part of a multimodal sensing garment. The sensors are arranged in addressable arrays for detection of spatial tactile pressure variation with a resolution of 1 mm or better. The sensors are fully conformable to nonplanar surfaces. A low-temperature hydrothermal process in conjunction with thermal nanoimprint lithography is demonstrated to achieve ordered growth of ZnO nanorods placed vertically on the flexible substrate. The nanorods are fully packaged in inert polyimide for protection against dust, moisture, and mechanical shock. The sensor response to applied pressure is observed to be nearly linear and with negligible hysteresis. A peak sensitivity of 21.2 μV/kPa has been observed for tactile pressure in the 10-200 kPa range.

As the demand for low-or no-power nano-sensors increases, new processing techniques gain importance to introduce novel sensing structures using well-known materials. ZnO presents substantial opportunities in this aspect due to its semiconducting and piezoelectric properties and ability to crystalize at relatively low temperatures. Many nanostructure configurations of ZnO can be easily synthesized, making it an ideal material for nano-sensors and nano-energy harvesters. This paper reviews design, fabrication and performance analysis of several nano-sensors and nano-energy harvesters based on ZnO. Several possible techniques are discussed that can further improve the performance of ZnO in these nano-sensors and nano-energy harvesters.

ZnO nanowires offer nanometer resolution with high piezoelectric coefficient as force sensors. There is, however, much room to improve the sensitivity with addition of substitutional impurities. Here, the effect of p-type Li doping on vertically-aligned crystalline piezoelectric ZnO nanowires (NWs) is investigated. The NWs are used as an elementary material to fabricate micro-Newton force sensors based on undoped and Li-doped ZnO nanostructures. The novelty of this work lies on the doping of ZnO NWs with Li that improves its performance by altering the physical and material properties. Scanning Electron Microscope (SEM) images illustrate that the force sensors can realize nanometer scale resolution. X-ray diffraction (XRD) and Raman spectroscopy depict that most of the Li atoms are incorporating into the ZnO structure as substitutional dopants, thus improving the piezoelectric properties. An Atomic Force Microscope (AFM) is operated in contact mode to apply pN range mechanical force to the nanowires. It is shown that the sensitivity of ZnO NW sensor increases from 0.033 mV/pN to 0.102 mV/pN when doped with Li.

A nanoelectromechanical vibrational energy harvester is reported based on a ZnO nanorod array coupled to a microelectromechanical mass-spring system. A carpet of vertically aligned crystalline zinc oxide nanorods grown using a low temperature process was characterized to determine their piezoelectric response to mechanical excitation. An atomic force microscope was operated in the force spectroscopy mode to probe ZnO nanorods applying a force in the µN range. In contrast to previously published reports using lateral tip motion (C-AFM), the motion of the AFM tip in our experiment was perpendicular to the plane of the nanorods, which closely mimics the operation of the bulk-micromachined NEMS energy harvester. Voltage pulses with amplitudes ranging from hundreds of µV to few mV were observed. The novelty of this work lies in the integration of the ZnO NEMS and Si-MEMS structures, the use of nanoimprint lithography to achieve periodic, vertical placement of the ZnO nanorods, and the demonstration of piezoelectric voltage generation through low-temperature processed ZnO nanorod carpet.

MEMS force sensors embedded in flexible polyimide substrates are reported, motivated by the need to monitor force and pressure on nonplanar surfaces for structural health monitoring. Details of the fabrication, measured preliminary results, and figures of merit are described. The sensors showed an average piezoresistive gauge factor of 1.75. The average value of normalized Hooge noise coefficient K1/f was found to be 1.89×10-10. The sensitivity was measured to the range from 0.266 to 2.248 V/N with an average sensitivity of 1.25 V/N. The noise equivalent force was calculated to the range from 8.83 to 46.56 μN with an average value of 20.47 μN for the force sensors in a noise frequency bandwidth from 1 to 8 Hz.

Piezoresistive NiCr tactile sensors have been developed on surface micromachined aluminum oxide membranes, embedded between two polyimide layers, i.e., one serving as a substrate, another as a superstrate. A novel method to bond a flexible superstrate polyimide layer onto a microelectromechanical system tactile sensor array is presented. The piezoresistors were connected in a half-Wheatstone bridge configuration to minimize the effects of thermal drift. Three different types of sensor designs were fabricated and characterized to obtain the nichrome thin-film gauge factor. The experimental results were compared with those simulated for the same conditions of membrane deflection. The gauge factors range between 2.2 and 7.9 for sensors with a superstrate and between 1.5 and 3.2 without a superstrate.

A physics-based model has been implemented to describe the low-frequency noise behavior in differently processed reduced-surface-field lateral double-diffused MOS devices. The developed model is based upon the correlated carrier number and the mobility fluctuation theory known as the unified model but has been modified to account for the fluctuations in the extended drain and the channel. Unlike the unified 1/f noise model, nonuniform trap distribution has been taken into account with respect to position in the gate oxide and band-gap energy. The effect of stress on dc and noise characteristics has been investigated. Individual resistance and noise components in the channel and in the extended drain regions under the gate and field oxides are evaluated as a function of stress duration. The model is experimentally verified to identify the physical mechanisms for degradation due to stressing.

A z-direction electret based Silicon-On-Insulator (SOI) electrostatic energy harvester (EH) that uses both out-of-plane overlap and out-of-plane gap closing capacitor is designed. A mathematical model of the system is developed and solved using MATLAB ordinary differential equation solver and ten design parameters are optimized to maximize the average output power using Pattern Search algorithm of MATLAB's optimization toolbox. The device with a dimension of 6600 μm by 4225 μm by 125 μm is capable to harness a power density of 31 nW/cm3 for an input vibration source of 1g and frequency of 120 Hz operated at 0.1 atmospheric pressure. A combination of meander and fixed-fixed springs are designed to obtain required spring constant and resonance at desired frequency. Finally, the optimized system is built using CoventorWare and modal harmonic analysis is performed which depicted the primary mode to have resonance at the desired frequency.

This paper presents the fabrication and measured performance of temperature sensors embedded in flexible polyimide substrates. The sensing material used for the temperature sensor was undoped amorphous silicon which was fabricated on a 35-m-thick layer of polyimide that serves as the flexible substrate. Another flexible polyimide superstrate layer of 35-40 m was spin-coated on top of the sensors to make sure the temperature sensors lie on a zero stress plane. The temperature coefficient of resistance was measured over the temperature range of 200- 360 K. The maximum temperature coefficient of resistance at 30 C was measured to be 0.0288 K-1. The effect of the flicker noise and voltage dependence of the voltage noise power spectral density exhibited by the sensor was evaluated. The normalized flicker noise coefficient was found to be 1.2 × 10-11.

Capacitive accelerometers were designed, fabricated and characterized on Si and flexible polyimide substrates with sensitivities ranging between 8.9-23 fF/g and 2.5-9.2 fF/g for z-axis and lateral axes, respectively. UV-LIGA process in conjunction with Ni electroplating was utilized to form the proof mass. Measured sensitivities on the flexible accelerometers were higher than the predictions of the simulations, ranging between 22-27 fF/g in the z axis and 12-18 fF/g in the lateral axes, respectively.

A low-temperature deposition process employing aluminum-induced crystallization has been developed for fabrication of piezoresistive polycrystalline silicon (polysilicon) films on low cost and flexible polyimide substrates for force and pressure sensing applications. To test the piezoresistive properties of the polysilicon films, prototype pressure sensors were fabricated on surface-micromachined silicon nitride (Si 3 N 4 ) diaphragms, in a half-Wheatstone bridge configuration. Characterization of the pressure sensor was performed using atomic force microscope in contact mode with a specially modified probe-tip. Low pressure values ranging from 5 kPa to 45 kPa were achieved by this method. The resistance change was found to be − 0.1% to 0.5% and 0.07% to 0.3% for polysilicon films obtained at 500 °C and 400 °C, respectively, for the applied pressure range.

Nanocrystalline piezoresistive polysilicon films were obtained at low temperatures by aluminum-induced crystallization (AIC). The films exhibited granular structure with good polycrystalline properties. A piezoresistive pressure sensor was fabricated on a polyimide substrate, in a Wheatstone bridge configuration comprising two passive resistors and two active piezoresistors made of polysilicon films obtained by AIC. The resistors showed linear I-V characteristics with typical resistance values between 15 and 30 kΩ . Atomic force microscopy was used in contact mode to study the response of the pressure sensor with applied pressure in the 2-19 kPa range. For the higher range of 450 kPa-2 MPa, a load-cell with a nanopositioner was utilized. The pressure-sensor sensitivity was measured to be 41.12 and 5.02 mV/MPa, respectively, for these ranges, when the Wheatstone bridge was bias at 1 V.

For specific RF applications, where the use of MEMS is highly attractive, cost-effective reliable packaging is one of the primary barriers to commercialization. Many RF MEMS devices require a hermetic or vacuum operation environment. This paper presents a post-CMOS-compatible method for vacuum packaging of RF MEMS devices by growing an encapsulation layer during the device fabrication. The resulting MEMS devices are surrounded by a vacuum cavity and can then be placed in a conventional low-cost circuit package. This is a low-temperature area-efficient device-level encapsulation for MEMS devices. RF MEMS resonators in a fixed-fixed configuration were used as the test bed since their quality factor can be used as a measure of the package quality. The encapsulation process is based on a double-sacrificial-layer surface micromachining technique, which is used to create a cavity under and above the resonator. Polyimide was used as the sacrificial layer, followed by the deposition of a packaging layer with trench cuts, which facilitate the sacrificial layer removal. The trench cuts were then sealed at a low pressure, forming a cavity around the device at the sealant layer deposition pressure. Extensive RF characterization and reliability tests were performed on the packaged resonators.

Understanding and minimization of degradation in new generation MOSFETs from stress-induced traps in high-k gate dielectrics is of critical importance. Towards this purpose, high-k dielectrics were subjected to accelerated hot carrier and constant voltage stress. The generated traps and the additional 1/f noise observed in the MOSFET characteristics were evaluated. The nMOSFETs had HfSiON gate dielectric and TiN metal gate. Nitridation of HfSiO gate dielectric MOSFETs was achieved by either high temperature NH3 anneal or lower temperature plasma anneal. For comparison purposes, pure HfSiO samples were also included in the study. Influence of different dielectric nitridation procedures on the stress-induced degradation of transconductance, threshold properties and low-frequency noise was studied. Worst degradation conditions, Vg=Vd were used for hotcarrier stress, whereas for constant voltage stress the vertical field was fixed at 10 MV/cm for all transistors to achieve comparable stressing conditions. Among three differently processed samples, thermally nitrided device showed most degradation in its saturation drain current, maximum transconductance and threshold voltage compared to the plasma nitrided and pure HfSiO samples. This higher degradation in thermally and plasma nitrided HfSiON is attributed to the presence of nitrogen. Forward and reverse mode noise behavior after HCS for 1000s is shown in Fig. 1. For plasma nitrided sample, the increase in noise in higher frequency range implies that increased trap density close to the high-k/Si interface is more dominant due to HCS than thermally nitrided and pure HfSiO samples, whereas increased noise in the lower frequency range region for the plasma nitrided sample points to the traps further into the dielectric. This is consistent with the observed shift in Vth for the thermally nitrided samples with HCS, implying bulk degradation of the dielectric and therefore increased noise at lower frequencies. The MOSFETs were also subjected to constant voltage stress (CVS), applied at the gate terminal for 1000s while source, drain and substrate terminals were grounded. Fig. 2 shows the drain voltage noise power spectral density for three different samples. For plasma nitrided HfSiON and HfSiO devices, there is a slight increase in noise. However, the thermally nitrided sample showed an order of magnitude increase in noise. This might be due to the electrons filling the existing traps and increased charge damages created during the CVS. For the thermally nitrided sample, high concentration of nitrogen at the interface as well as damage near HK/metal gate stack due to CVS causes higher noise. Moreover, oxygen vacancies are also likely candidates for intrinsic electron traps in devices and threshold voltage instability. In plasma-assisted nitridation, atomic nitrogen is introduced in to the system. This nitrogen incorporation into oxygen vacancy sites results in lowering of the defect level and making them less active as electron traps, whereas thermal nitridation in NH3 ambient at high temperatures results in a higher concentration of protons, leading to an increment in positive charge centers and noise due to Coulomb scattering from these centers. This work is partially supported by SRC 2004-VJ-1193. We would like to thank Texas Instruments for MOSFETs.

Understanding and minimization of low-frequency noise (LFN) originating from high- k (HK) gate dielectrics in new generation MOSFETs are of critical importance to applications in RF, analog, and digital circuits. To understand the effect of stress conditions on noise, nMOSFETs were subjected to accelerated hot-carrier stress (HCS) and positive constant-voltage stress (CVS). The additional LFN introduced through stressing was evaluated on nMOSFETs with TiN metal gate and HfSiON gate dielectric. Nitridation of HfSiO gate-dielectric MOSFETs was achieved by either a high-temperature NH3 anneal or a lower temperature plasma anneal. Influence of different dielectric nitridation procedures on the stress-induced degradation of transconductance, threshold properties, and LFN was studied. Worst degradation conditions, i.e., Vg = Vd, were used for HCS, whereas for CVS, the vertical field was fixed at 10 MV/cm for all transistors to achieve comparable stressing conditions. Plasma-nitrided devices showed less increase in their noise in the linear operation region than the thermally nitrided devices. This difference in noise behavior is attributed to the nitrogen profile across the HK/Si interface and in the bulk of the HK oxide caused by different nitridation techniques. The dielectric defect profile resultant from different annealing techniques was consistent with the spectral form of the observed drain-voltage LFN.

A new unified noise model is presented that accurately predicts the low-frequency noise spectrum exhibited by MOSFETs with high dielectric constant (high- k ), multi-stack gate dielectrics. The proposed multi-stack unified noise (MSUN) model is based on number and correlated mobility fluctuations theory developed for native oxide MOSFETs, and offers scalability with respect to the high- k /interfacial layer thicknesses. In addition, it incorporates the various electronic properties of high- k /interfacial layer materials such as energy barrier heights between different gate layers, and dielectric trap density with respect to band energy and position in the dielectric. For verification of the new model, the low-frequency noise, DC and conventional split C–V measurements were performed in the 78–350 K temperature range on TaSiN/HfO 2 n-channel MOSFETs. The interfacial layer in these devices was either thermal SiO 2 by Stress Relieved Pre-Oxide (SRPO) pretreatment or chemical SiO 2 resulting from standard RCA (Radio Corporation of America) clean process. Using the experimental noise data, the channel carrier number fluctuations mechanism was at first established to be the underlying mechanism responsible for the noise observed at all temperatures considered. Secondly, the normalized noise exhibited a weak dependence on temperature implying that the soft optical phonons, although known to result in mobility degradation, have no effect on the noise characteristics in these high- k gate stack MOSFETs. Finally, the new model was shown to be in excellent agreement with the measured noise in 1–100 Hz frequency range at temperatures of 78–350 K for both gate stacks.

A physics-based low frequency noise model has been developed for MOSFET devices with nitrided high- κ gate dielectric materials. The new model is built upon the correlated carrier number and surface mobility fluctuations theory, where the original Unified Model was modified to take into account the multilayered structure of the high- κ gate dielectrics, and the resultant charge carrier tunneling process in terms of a two-step cascaded barrier instead of a single step barrier. The new model eliminates the discrepancies previously reported for the dielectric trap density values extracted from noise data using the original Unified Model for flicker noise. The dielectric trap density, typically taken as an average or spatially uniform in the dielectric and constant with respect to energy, is replaced here with an exponential expression dependent on the band-gap energy along with a spatial distribution of the traps in the high- κ layer. Thus, due to the energy dependence of the trap density, bending of the energy bands induces an additional non-uniformity in the spatial trap distribution. Implementation of this expression also provides the much needed flexibility in simulating realistic trap profiles in high- κ materials. Here, MOSFETs with nitrided dielectrics were considered for the noise experiments, as nitridation presents many advantages for the electrical and thermal characteristics of the gate insulator. Variable temperature low frequency noise and mobility measurements have been performed on MOSFETs with nitrided high- κ dielectric. Phonon scattering was found to have a profound effect on the mobility behavior, but no consequence on the low frequency noise characteristics. The low frequency noise data obtained on devices with different interfacial layer thicknesses and different regions of transistor operation was successfully compared with the predictions of the newly developed Multi Stack Unified Noise (MSUN) Model over a temperature range of 172–300 K.

Low frequency noise measurements were performed on n- and p-channel MOSFETs with TaSiN and TiN metal gates, respectively, deposited on ALD HfO2 gate dielectric. Lower normalized current noise power spectral density is reported for these devices in comparison to poly-Si/HfO2 devices and that yielded one order lower magnitude for extracted average effective dielectric trap density. In addition, the noise levels in PMOS devices were found to be higher than NMOSFETs and the dielectric trap distribution less dense in the upper mid-gap than the lower mid-gap region. The screened carrier scattering coefficient extracted from the noise measurements was approximately the same for metal and poly-Si high-k stacks but higher than that for the poly-Si SiO2 system, implying higher Coulomb scattering effects. It is believed that the elimination of dopant penetration seen in poly-Si system and low thermal budgets for metal gate deposition helped lower the noise magnitude and yielded better mobility and effective trap density values.

This paper reports on the design, fabrication, and characterization of device-level vacuum-packaged microbolometers on rigid Si wafers and flexible polyimide substrates. Semiconducting yttrium barium copper oxide (commonly, referred to as YBCO) serves as the bolometric material. Operating micromachined bolometers in vacuum reduces the thermal conductance G(th) from the detector to the substrate. If flexibility of the substrate is not to be sacrificed, then the vacuum packaging needs to be done at the device level. Here, the microbolometers are fabricated on a silicon nitride support membrane, isolated from the substrate using surface micromachining. Suitable materials as well as various dimensions in the vacuum cavity are determined using finite-element method (FEM)-based CoventorWARE. A vacuum cavity made of Al2O3 has been designed. The thermal conductance G(th) of bolometers with the geometry implemented in this work is the same for devices on rigid and flexible substrates. The theoretical value of G(th) was calculated to be 4.0 x 10(-6) W/K for devices operating in vacuum and 1.4 x 10(-4) W/K for devices operating at atmospheric pressure. Device-level vacuum-packaged microbolometers on both rigid Si and flexible polyimide substrates have been fabricated and characterized for optical and electrical properties. A low thermal conductance of 1.1 x 10(-6) W/K has been measured six months after fabrication, which implies an intact vacuum cavity.

This paper presents the design, fabrication process and characterization of a self-packaged MEMS accelerometer on a flexible substrate. The novelty lies in that the accelerometer is fabricated in between a polyimide substrate and a superstrate, thus allowing front-end encapsulation and bonding without the need for rigid packages. Modeling and optimization were done using Coventorware® software, where the designed structures were subjected to 6 cm-radius curvature, and the resulting stress was evaluated for each layer. Then, based on the simulated designs, a low-temperature fabrication process flow was developed using a double UV-LIGA fabrication technique in conjunction with surface micromachining. This novel technique allowed us to decouple the thicknesses of the proof-mass and the springs, thus attaining high sensitivity. Our experimental results indicate a sensitivity of about 125 fF/g at the resonant frequency for device size of 640 μm × 640 μm. The response from the device was two orders of magnitude higher than the noise. The resolution of the device was measured to be 150 millig in the range between −10g and +10g.

The fabrication and characterization of piezoelectric, ultra-thin (∼300 nm) aluminum nitride (AlN) cantilevers are reported. The novel flexible, ultra-thin film AlN provides excellent compatibility for flexible sensors. Tri-layer cantilevers were fabricated with the AlN layer being sandwiched between two metal electrode layers. Low deposition temperature (300 °C) was maintained to deposit the AlN by the DC reactive magnetron sputtering for superior CMOS and flexible substrate compatibility. The characterization of AlN cantilevers was performed using dynamic signal analyzer to measure the output voltage due to piezoelectricity. The output voltage for different cantilevers measured experimentally range from 3.69×10−5 V to 4.48×10−4 V and the experimental Johnson noise floor range from 7.23×10−12 V2/Hz to 6.9×10−8 V2/Hz. The corresponding power spectral densities range from 5.70×10−9 V2/Hz to 2.14×10−6 V2/Hz. The ultra-thin AlN cantilever structure forms the basis for future flexible force/pressure sensors, accelerometers, and energy harvesters.

A novel piezoelectric micro-energy generator is presented, which converts the mechanical vibrations into electricity by utilizing the piezoelectric effect of zinc oxide nanowires (ZnO NW). This is the first time an integrated energy harvester is built where vertically standing NWs are directly coupled to a MEMS proof-mass for maximum conversion of the vibration energy while maintaining the size in the order of hundreds of micrometers. Hydrothermal growth of nanowires combined with MEMS surface micromachining technology and LIGA is employed to fabricate the device. Patterned SU-8 photoresist confines the growth area of the NW block, located between the silicon substrate and a suspended silicon nitride membrane, on which a nickel proof-mass is electroplated. A piezoelectric potential between the two ends of the NW block is formed once compressed by the membrane due to external vibration. A maximum power of 42 pW across 5.5 MΩ load is measured at the vibration frequency of 40 Hz with an acceleration of 1.4g. The corresponding output voltage is 14.7 mV.

This paper presents a new statistical RTS model and a simulation tool to predict and replicate the RTS in time and frequency domains. This new developed RTS model and its simulation tool are constructed based on first-principles, taking into account Coulombic scattering effect, considering the non-uniformity in doping concentration in the channel and the non-uniformity in the trap distribution in the oxide, incorporating the effect of both linear and saturation regions of operation of MOSFETs, including the temperature effect on all temperature dependent parameters, and is fully scalable from single switching electron to ensembles 1/f noise. The RTS simulation (RTSSIM) generates the RTS in time domain based on the electrical properties that are associated with the identified trap. RTSSIM produces smooth transition from the RTS in time domain to 1/f noise and it takes into account the device scalability. The total power spectral density (PSD) for a number of active trap(s) less than 20 is computed directly from the generated RTS waveforms using Welch's PSD method. For 20+ active traps, RTSSIM evaluates the total PSD based on the summation of the RTS spectra.

This paper presents design, fabrication and measured performance parameters of micromachined infrared detectors on polyimide substrates. The detectors are of bolometer type made of semiconducting yttrium–barium–copper oxide (YBCO) as the thermometer material and are built on a 40–50m-thick layer of polyimide (PI5878G) that serves as a flexible substrate. A thin film of Si3N4 supports the detectors. Surface micromachining is used to isolate the detectors and the supporting nitride layer from the substrate. Despite being supported by a layer of Si3N4, an average thermal conductivity of 5.61 × 10 −7 W/K, comparable to self-supporting devices on flexible substrates has been measured. This opens the possibility of placing such flexible sensors on micromachined membranes, integrated with other functions such as pressure sensing to build “Smart Skin.” Roomtemperature responsivity of 7.4 × 10 3 V/W and detectivity of 6.6 × 10 5 cm Hz 1/2 /W were demonstrated on 40m × 40m microbolometers. The effect of substrate heating was also investigated and was found not to cause cross talk between the pixels. If these sensors are to be used as part of multi-functional, flexible sensor systems, device-level vacuum packaging is necessary. This was investigated using computer simulations for structural analysis and found to be feasible. © 2006 Elsevier B.V. All rights reserved.

This paper presents the design, modeling and simulation of micromachined, integrated pressure–thermal sensors on flexible polyimide substrates. Finite element simulations were performed with polycrystalline silicon as the piezoresistor material on a suspended Si3N4 layer. These piezoresistors are connected to each other in a half-bridge Wheatstone configuration using flexible aluminum interconnects. Several different designs of integrated thermal–pressure sensors as well as pressure-only sensors were simulated to compute the sensor figures of merit such as the percentage change in piezoresistance in response to normal pressure, piezoresistor Wheatstone-bridge output voltage for varying skin curvature, bolometric response to broadband infrared radiation, thermal time constant and thermal conductance of the micromachined structures hosting the sensors to the substrate. For a perpendicular uniform pressure application of 50 kPa, a maximum Wheatstone-bridge output of 7.59 mV was computed for 1 V bias, corresponding to a piezoresistance change of 1.52%. When the skin is bent to a curvature of 2.2 mm, a maximum Wheatstone-bridge output voltage of 70 mV was calculated for the case when the sensors are aligned along the axis of bending. Thermal and optical calculations performed on the integrated thermal–pressure sensors showed a thermal time constant as low as 12.8 µs for a 1.9 µm thick silicon nitride membrane layer, with a responsivity of 270 V W−1 to a broad-band infrared radiation. This would be appropriate for applications requiring fast response but not high sensitivity. Integrated sensors on a thinner silicon nitride membrane layer of 0.5 µm, on the other hand, exhibited responsivity as high as 2000 V W−1, with a response time of 626 µs.

In this paper, the effects of different transistor design aspects on the noise behavior of SiGe heterojunction bipolar transistors have been investigated. Selectively implanted collector, although retards the base push-out, does not deteriorate the noise characteristics. Moreover, a higher dopant implant in the extrinsic base region intended for a smaller base resistance does not deteriorate the noise characteristics. While the interface between the SiGe epitaxial and polycrystalline layers does not have any detrimental impact, the emitter-poly overlap significantly influences both the DC and the noise characteristics. Smaller emitter-poly overlap results in an increased non-ideal base current at lower bias voltages and produces appreciable generation–recombination noise. For all the transistors, except for the ones with smaller emitter-poly overlap, the base current noise power spectral density shows a near quadratic dependence on the base current, where the noise is believed to originate mostly from the superposition of the generation–recombination noise in the intrinsic emitter–base junction. The base current noise power spectral density for the transistors with a smaller emitter-poly overlap shows a near linear dependence on the base current, which results from an increased contribution from the trap-assisted tunneling fluctuations of the minority carriers at the surface of the emitter–base junction.

Low-frequency noise measurements and analysis were performed on n-channel MOSFETs with HfSiON as the gate-dielectric material. The role of SiON interfacial-layer thickness was investigated. It was observed that these fluctuations can be described by the unified flicker-noise model that attributes noise to correlated carrier-number/mobility fluctuations due to trapping states in the gate dielectric. The model was modified to include the effect of different gate stack layers on the observed noise. The carrier-number fluctuations were found to dominate over the correlated mobility fluctuations in the measured bias range and more so at the lower gate overdrives. The noise magnitude showed a decrease with increasing SiON interfacial-layer thickness. Furthermore, an inverse-proportionality relationship was revealed between the effective oxide trap density and SiON thickness.

Low-frequency noise characteristics are reported for TaSiN-gated n-channel MOSFETs with atomic-layer deposited HfO/sub 2/ on thermal SiO/sub 2/ with stress-relieved preoxide (SRPO) pretreatment. For comparison, control devices were also included with chemical SiO/sub 2/ resulting from standard Radio Corporation of America clean process. The normalized noise spectral density values for these devices are found to be lower when compared to reference poly Si gate stack with similar HfO/sub 2/ dielectric. Consequently, a lower oxide trap density of /spl sim/4/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ is extracted compared to over 3/spl times/10/sup 18/ cm/sup -3/eV/sup -1/ values reported for poly Si devices indicating an improvement in the high-/spl kappa/ and interfacial layer quality. In fact, this represents the lowest trap density values reported to date on HfO/sub 2/ MOSFETs. The peak electron mobility measured on the SRPO devices is over 330 cm/sup 2//V/spl middot/s, much higher than those for equivalent poly Si or metal gate stacks. In addition, the devices with SRPO SiO/sub 2/ are found to exhibit at least /spl sim/10% higher effective mobility than RCA devices, notwithstanding the differences in the high-/spl kappa/ and interfacial layer thicknesses. The lower Coulomb scattering coefficient obtained from the noise data for the SRPO devices imply that channel carriers are better screened due to the presence of SRPO SiO/sub 2/, which, in part, contributes to the mobility improvement.