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This article presents a 39 GHz transceiver front-end chipset for 5G multi-input multi-output (MIMO) applications. Each chip includes two variable-gain frequency-conversion channels and can support two simultaneous independent beams, and the chips also integrate a local-oscillator chain and digital module for multi-chip extension and gain-state control. To improve the radio-frequency performance, several circuit-level improvement techniques are proposed for the key building blocks in the front-end system. Furthermore, an advanced low-temperature co-fired ceramic process is developed to package the 39 GHz dual-channel transceiver chipset, and it achieves low packaging loss and high isolation between the two transmitting (TX)/receiving (RX) channels. Both the chip-level and system-in-package (SIP)-level measurements are conducted to demonstrate the performance of the transceiver chipset. The measurement characteristics show that the TX SIP provides 11 dB maximum gain and 10 dBm saturated output power, while the RX SIP achieves 52 dB maximum gain, 5.4 dB noise figure, and 7.2 dBm output 1 dB compression point. Single-channel communication link testing of the transceiver exhibits an error vector magnitude (EVM) of 3.72% and a spectral efficiency of 3.25 bit·s−1·Hz−1 for 64-quadrature amplitude modulation (QAM) modulation and an EVM of 3.76% and spectral efficiency of 3.90 bit·s−1·Hz−1 for 256-QAM modulation over a 1 m distance. Based on the chipset, a 39 GHz multi-beam prototype is also developed to perform the MIMO operation for 5G millimetre wave applications. The over-the-air communication link for one- and two-stream transmission indicates that the multi-beam prototype can cover a 5–150 m distance with comparable throughput.

Abstract A reactive matching (RM) power amplifier (PA) can achieve higher efficiency than a distributed amplifier (DA). In this paper, RM PAs that cover 18–40 GHz are proposed by using one‐order and two‐order synthesised transformer networks (STNs) with GaN on Si technology. In this band, the PAs can provide ≥30 dBm and ≥31.9 dBm output power, with power‐added efficiency (PAE) of ≥17% and ≥15% in the continuous mode, respectively. Further, STNs are analysed using the transmission poles method (TPM) instead of the resonant frequency method (RFM). Thus, the limitations of output power and bandwidth are comprehensively derived. In the one‐order STN, the impedance transformation ratio (T1N) has a maximum value (TMAX_1N), limiting the output power. A two‐order STN is proposed, and the impedance transformation ratio maximum (TMAX_2N) can be improved to (TMAX_1N)2. The result of this paper will be helpful for wideband high‐power amplifier applications.

This paper presents a 6-bit vector-sum phase shifter with half-quadrant control technique for Ku-band phased arrays. In this paper, the gain and phase symmetry in each quadrant is studied. Based on the gain and phase symmetry in vector-sum phase shifter, the half-quadrant control technique is proposed to simplify the complexity of phase control, phase measurement and phase calibration for large-scale phased arrays. Besides, a phase optimization method without extra phase settings is proposed to achieve low phase error. As results, the measured 6-bit RMS phase error is 1.6° ~ 2.3° across 13 ~ 17 GHz with only 64 different phase states, demonstrating the brevity and accuracy of phase control simultaneously. With the same phase optimization, six chips are measured and the maximum deviation of RMS phase error is -11.4 dBm. The chip consumes 29.7 mW with 1.8 V supply and occupies $0.9\times1.45$ mm2. This work is fabricated in TSMC 180-nm CMOS technology.

This paper presents a high linearity and low noise mixer for millimeter-wave applications in 65-nm CMOS process. A noise-reduction transformer with harmonic suppression is utilized and inserted between transconductance stage and switch stage to improve the linearity and noise figure (NF). Benefitted from the transformer-coupling cascode topology, the mixer can operate at a low supply voltage without sacrificing the linearity. In addition, this topology provides a great freedom for the choice of biases in transconductance stage and switch stage. Thus, linearity and noise performance can be further improved by optimizing the bias conditions of the two stages. According to experimental results, the proposed mixer exhibits a maximum conversion gain of 9.5 dB and a minimum single sideband NF of 9.2 dB with a local oscillator (LO) power of -3 dBm. The 3-dB bandwidth ranges from 62 to 90 GHz. The input 1-dB compression point (P1 dB) is -3.8 dBm at 77 GHz. Due to the compact and fully symmetrical layout, the LO-to-RF isolation is better than 48 dB.

This paper proposes a variable gain amplifier (VGA) with reconfigurable DC-offset cancellation (DCOC) for multi-standard applications. In this design, a cell-based design method and some bandwidth extension technologies are adopted to achieve a high data rate and a wide gain control range simultaneously. In addition, the DCOC having a tunable lower-cutoff frequency can make an optimum compromise between BER and SNR according to the specified baseband standard. The measurements show that the VGA achieves a gain control range from -6 dB to 60 dB, a bandwidth beyond 3 GHz, and a tunable lower-cutoff frequency from 0 to 300 kHz. When entering a 223-1 pseudo-random bit sequence signal at 5 Gb/s, the VGA consumes 17 mW from a 1.2-V supply and the output data peak-to-peak jitter is less than 40 ps. The VGA is fabricated in a 90-nm CMOS process with a chip size (including all pads) of 0.52 × 0.5 mm2.

A fully integrated Ku-band transmit/receive (T/R) switch based on a two-stage equivalent transmission line structure has been designed using a 180-nm complementary metal-oxide-semiconductor (CMOS) process. An analysis shows a relation between the series inductance and turn-on resistance for high isolation. A stack structure with feed-forward capacitors was chosen as a means of improving the power-handling capability of the switch. A low insertion loss (IL) of the switch was achieved by eliminating series transistors. The measured minimum ILs of the switch in the transmitter (TX) and receiver (RX) modes are 2.7 dB and 2.3 dB, respectively. The measured isolations in the TX and RX modes are greater than 34 and 25 dB, respectively, from 15 to 18 GHz. The design reaches a measured input 1-dB power compression point (IP1dB) of 22 dBm at 17 GHz. The switch achieves stringent isolation, insertion loss, and power-handling capability requirements along with the capability of full integration, demonstrating its great potential for use in fully integrated CMOS T/R chips.

The impedance at the each input terminal of paper presents a voltage combining Doherty power amplifier in a standard 180-nm CMOS process. This Doherty PA uses a series combining transformer (SCT) to combine the output power and realize the load modulation, which is different from the conventional current combining method. The series combining transformer is analyzed for impedance modulation behavior, and we have provided the design method. The proposed Doherty PA achieves a maximum output power of 27.6 dBm at 1.75 GHz with a peak power added efficiency (PAE) of 35.2% at 3.4 V supply voltage. The PAE at 6 dB back-off is still high, about 29.2%. The PA has 24.2 dBm output power with 30.2% PAE at -37 dBc ACLR (5 MHz offset) and 25.2 dBm output power with 32% PAE at -33 dBc ACLR (5 MHz offset) at 1.75 GHz under a wideband code division multiple access signal with 3.3-dB PAPR and 3.84-MHz BW.

This paper deals with the fabrication of an inductorless wideband low-noise amplifier (LNA). The LNA includes two branches in parallel: a common-source (CS) path and a common-gate (CG) path. The CS path is responsible for providing enough power gain, while the CG path is used to achieve the input impedance matching. To eliminate the noise contribution of the CG path, the noise cancellation technique is applied. Therefore, the overall noise figure (NF) is improved. The phase mismatch between the two paths is also quantitatively analyzed to investigate its effect on gain and NF. The analytical results agree well with the simulation results. The LNA has been fabricated by a commercial 0.18-μm CMOS process. The measurement results show that the LNA has achieved a maximum gain of 14.5 dB with 1.7-GHz 3-dB gain bandwidth and a minimum NF of 3 dB. The tested input 1-dB gain compression point (IP1 dB) is -10.4 dBm at 1 GHz and the input third-order intercept point is 0.25 dBm. With 1.8-V supply, the LNA draws only 6-mA dc current.

This work was supported in part by the National Science and Technology Major Project, Ministry of Science and Technology of China, under Grant 2016ZX03001015-004, in part by the Scientific Research Foundation for the Returned Overseas Chinese Scholars State Education Ministry under Grant M16010201LXHG5002, and in part by the Fundamental Research Funds for the Central Universities under Grant ZYGX2015KYQD006.

The permittivity and conductivity of chemical vapor deposited monolayer graphene are investigated up to 40 GHz. The characterization method is based on a coplanar waveguide transmission line structure that is fabricated on a multilayer substrate of Si/SiO2/graphene/Al2O3 from the bottom up. The effective relative permittivity of the coplanar waveguide transmission line is extracted using Thru-Reflect-Line calibration and scattering parameter measurements, and then the relative permittivity and corresponding conductivity of graphene are characterized using partial capacitance techniques. The results demonstrate that the conductivity and sheet resistance are remarkably frequency-dependent and that the complex relative permittivity is consistent with the Drude model.

An improved empirical large signal model for 0.1 µm AlGaN/GaN high electron mobility transistor (HEMT) process is proposed in this paper. The short channel effect including the drain induced barrier lowering (DIBL) effect and channel length modulation has been considered for the accurate description of DC characteristics. In-house AlGaN/GaN HEMTs with a gate-length of 0.1 μm and different dimensions have been employed to validate the accuracy of the large signal model. Good agreement has been achieved between the simulated and measured S parameters, I-V characteristics and large signal performance at 28 GHz. Furthermore, a monolithic microwave integrated circuit (MMIC) power amplifier from 92 GHz to 96 GHz has been designed for validation of the proposed model. Results show that the improved large signal model can be used up to W band.

A new microstrip bandpass filter using composite right/left-handed (CRLH) mushroom structure with interdigital capacitors and defected ground structure (DGS) is proposed. The proposed filter uses CRLH mushroom structure working at its first negative resonance mode to create the passband and DGS to increase rejection outside the passband. Simulation and measurement results are in good agreement, and low in-band insertion loss and great out-band rejection have been achieved. It is demonstrated that the combination of CRLH mushroom structure with interdigital capacitors and DGS has succeeded in achieving excellent performance. This new filter can be applied in transmitting and receiving antennas.