Analysis and Design of CMOS Doherty Power Amplifier Based on Voltage Combining Method

The impedance at the each input terminal of paper presents a voltage combining Doherty power amplifier in a standard 180-nm CMOS process. This Doherty PA uses a series combining transformer (SCT) to combine the output power and realize the load modulation, which is different from the conventional current combining method. The series combining transformer is analyzed for impedance modulation behavior, and we have provided the design method. The proposed Doherty PA achieves a maximum output power of 27.6 dBm at 1.75 GHz with a peak power added efficiency (PAE) of 35.2% at 3.4 V supply voltage. The PAE at 6 dB back-off is still high, about 29.2%. The PA has 24.2 dBm output power with 30.2% PAE at -37 dBc ACLR (5 MHz offset) and 25.2 dBm output power with 32% PAE at -33 dBc ACLR (5 MHz offset) at 1.75 GHz under a wideband code division multiple access signal with 3.3-dB PAPR and 3.84-MHz BW.