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Bilateral chronic Achilles tendon rupture is a rare condition which is commonly associated with a predisposing factor such as long-term steroid therapy. Treatment of such patients requires special consideration since tendon fibers are usually weak due to steroid therapy and tendon ends are retracted. However, no consensus is available regarding the optimal surgical procedure. Ambulation after surgery is another problem; according to the literature, patients usually wore casts bilaterally and were kept non-weight bearing for several weeks after surgery, which means patients were usually not able to walk for several weeks after surgery. We present the case of bilateral chronic Achilles tendon ruptures in a patient on steroid therapy, which provided achievement of a good functional outcome with 1-year follow up through Achilles tendon reconstruction and early functional rehabilitation. This rehabilitation included starting to walk the day after surgery using patellar tendon bearing braces with wedges.

Ferroelectricity and crystallinity of TiN/ZrO2/HfxZr1−xO2 (Hf:Zr = 0.43:0.57; HZO)/SiO2/Si metal–ferroelectric–semiconductor (MFS) capacitors with a top ZrO2 nucleation layer fabricated by low-temperature processes at 300 °C of atomic layer deposition and post-metallization annealing (PMA) were systematically investigated. The HZO (10 nm)-based MFS capacitors without (w/o) and with 2- and 10-nm-thick ZrO2 films (ZrO2-2 nm and ZrO2-10 nm, respectively) were found to form an extremely thin SiO2 interfacial layer (SiO2-IL) with a thickness of one or two monolayers. The HZO film in the TiN/ZrO2/HZO/SiO2/Si capacitors formed the ferroelectric orthorhombic phase even with a low thermal budget of 300 °C; in contrast, that of the w/o capacitor exhibited a predominantly amorphous structure. This result is attributed to the polycrystalline ZrO2 film acting as a nucleation layer for the crystallization of an amorphous HZO film during PMA treatment. Therefore, the remnant polarization (2Pr) increased in the order of w/o (2.2 µC/cm2) < ZrO2-2 nm (6.8 µC/cm2) < ZrO2-10 nm (15 µC/cm2). The endurance properties of the ZrO2-10 nm capacitor were free from the wake-up effect and exhibited less degradation because of the insertion of a thick ZrO2 film of 10 nm at the TiN/HZO interface, which promoted the preferential formation of the ferroelectric orthorhombic phase and prevented the formation of oxygen vacancies at the ZrO2/HZO interface. These results suggest that superior ferroelectricity with wake-up-free properties and higher fatigue resistance of HZO-based MFS capacitors can be achieved by a low-temperature fabrication technique (300 °C) using a top ZrO2 nucleation layer.

We have examined impacts of gate insulator (Al2O3 or HfO2) and gate electrode (TiN or W) on electrical performance of ZnSnO/Si bilayer tunneling field-effect transistors (TFETs). It is found from the capacitance-voltage (C-V) characteristics that the W gate is effective to reduce the counter-clockwise hysteresis. Additionally, the optimal temperature of post-metallization annealing (PMA) is different for each gate stack, and this optimization is critically important for the high ON-state current (ION) and steep ON/OFF switching. The W/Al2O3/ZnSnO/Si bilayer TFET provides the hysteresis-free steep ON/OFF switching with the minimum sub-threshold swing (SS) of 65.4 mV/dec. and average SS of 72.0 mV/dec. in a gate-voltage swing of 0.3 V, which are 19% and 18% lower than the control TiN/Al2O3/ZnSnO/Si bilayer TFET. When the gate stack is replaced by W/HfO2/Al2O3, the TFET exhibits less steep ON/OFF switching in spite of thinning capacitance equivalent thickness (CET) from 5.9 and 2.3 nm. These results indicate the importance of improvement in the gate stack quality on the sub-threshold characteristics of the bilayer TFETs.

This paper demonstrates that the electrical properties of suspended graphene nanomesh (GNM) can be tuned by systematically changing the porosity with helium ion beam milling (HIBM). The porosity of the GNM is well-controlled by defining the pitch of the periodic nanopores. The defective region surrounding the individual nanopores after HIBM, which limits the minimum pitch achievable between nanopores for a certain dose, is investigated and reported. The exponential relationship between the thermal activation energy (EA) and the porosity is found in the GNM devices. Good EA tuneability observed from the GNMs provides a new approach to the transport gap engineering beyond the conventional nanoribbon method.

The effect of post-implantation annealing (PIA) on Al–N isoelectronic trap (IET) formation in silicon has been experimentally investigated to discuss the Al–N IET formation and implantation-induced defect recovery mechanisms. We performed a photoluminescence study, which indicated that self-interstitial clusters and accompanying vacancies are generated in the ion implantation process. It is supposed that Al and N atoms move to the vacancy sites and form stable Al–N pairs in the PIA process. Furthermore, the PIA process recovers self-interstitial clusters while transforming their atomic configuration. The critical temperature for the formation/dissociation of Al–N pairs was found to be 450 °C, with which we describe the process integration for devices utilizing Al–N IET technology.

The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (Vt) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al2O3 blocking layer instead of a SiO2 blocking layer. It was also confirmed that the variability of Vt before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials.

A threshold voltage (Vth) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate have been investigated. It is revealed that the Vth of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling between the Si channel and the back gate. We have also carried out analysis of the Vth controllability in terms of the size dependence such as the gate length (LG) and the fin width (TFin).