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This paper presents a fully integrated CMOS humidity sensor for a smart RFID sensor platform. The sensing element is a CMOS-compatible capacitive humidity sensor, which consists of top-metal finger-structure electrodes covered by a humidity-sensitive polyimide layer. Its humidity-sensitive capacitance is digitized by an energy-efficient capacitance-to-digital converter (CDC) based on a third-order delta-sigma modulator. This CDC employs current-efficient operational transconductance amplifiers based on current-starved cascoded inverters, whose limited output swing is accommodated by employing a feedforward loop-filter topology. A programmable offset capacitor is included to remove the sensor's baseline capacitance and thus reduce the required dynamic range. To reduce offset errors due to charge injection of the switches, the entire system is auto-zeroed. The proposed humidity sensor has been realized in a 0.16- μm CMOS technology. Measurement results show that the CDC performs a 12.5-bit capacitance-to-digital conversion in a measurement time of 0.8 ms, while consuming only 8.6 μA from a 1.2-V supply. This corresponds to a state-of-the-art figure-of-merit of 1.4 pJ/conversion-step. Combined with the co-integrated humidity sensing element, it provides a resolution of 0.05% RH in the range from 30% RH to 100% RH while consuming only 8.3 nJ per measurement, which is an order-of-magnitude less energy than the state-of-the-art.

We analyze in detail the requirements for the detailed physical modeling of nanoscale MOSFETs and show that Schro/spl uml/dinger drift-diffusion per subband simulations are adequate for the inverse modeling of bulk-Si MOSFETs with gate length down to 40 nm (channel length down to 26 nm) from their dc electrical characterization. We show that a proper treatment of quantum effects both in the channel and in the polysilicon gate through the direct solution of Schro/spl uml/dinger equation, and a transport model based on two-dimensional subbands are required for accurate and-after calibration-predictive modeling. The model is included in the NANOTCAD2D code (Curatola and Iannaccone, 2003). We also evaluate the performance gap to ballistic transport, by comparing the experiments with simulations based on a fully ballistic transport model on the devices structures extracted with the inverse modeling procedure.

Sheet resistivity and Hall measurements have been performed on a series of p-type modulation-doped Si/Si1−xGex heterostructures. The structures were grown by a production-compatible atmospheric-pressure chemical-vapor deposition technique and all the epitaxial layers were lattice matched to the silicon substrates. A depleted-doping technique was used to supply the quantum well with holes, and this approach has enabled the transport properties of the SiGe layers to be characterized between 4.2 and 295 K. Measurements of the Hall scattering factor and drift mobility are reported for ultrathin, high-Ge content layers (0.3

We present here a novel approach to CMOS fabrication based on advanced lateral channel doping profiling technique coupled to gate workfunction engineering. The performance of this technology for both digital and analog applications is evaluated in detail to illustrate that it satisfies the requirements for mixed digital-analog circuitry. The use of asymmetric source/drain lateral profiles proves to be especially beneficial to analog applications.

The use of polycrystalline SiGe as the gate material for deep submicron CMOS has been investigated. A complete compatibility to standard CMOS processing is demonstrated when polycrystalline Si is substituted with SiGe (for Ge fractions below 0.5) to form the gate electrode of the transistors. Performance improvements are achieved for PMOS transistors by careful optimization of both transistor channel profile and p-type gate workfunction, the latter by changing Ge mole fraction in the gate. For the 0.18 /spl mu/m CMOS generation we record up to 20% increase in the current drive, a 10% increase in the channel transconductance and subthreshold swing improvement from 82 mV/dec to 75 mV/dec resulting in excellent "on"/"off" currents ratio. At the same time, NMOS transistor performance is not affected by gate material substitution.

Ion implantation has been used to realize non-uniform, steep retrograde (SR) dopant profiles in the active channel region of advanced Si MOSFET’s. After defining the transistor configuration, SR profiles were formed by dopant implantation through the polycrystalline Si gate and the gate oxide (through-the-gate, TG, implantation). The steep nature of the as-implanted profile was retained by applying rapid thermal annealing for dopant activation and implantation damage removal. For NMOS transistors, TG implantation of B yields improved transistor performance through increased carrier mobility, reduced junction capacitances, and reduced susceptibility to short-channel effects. Electrical measurements show that the gate oxide quality is not deteriorated by the ion-induced damage, demonstrating that transistor reliability is preserved. For PMOS transistors, TG implantation of P or As leads to unacceptable source/drain junction broadening as a result of transient enhanced dopant diffusion during thermal activation.

A novel approach to the super-steep retrograde (SSR) channel profile formation for MOSFETs is suggested, with dopant implantation in the late stages of the processing, with the gate, source/drain already in place ("TGi"). Only a single damage/activation anneal and the back-end thermal budget are experienced by the implanted dopants, which results in steep profiles even when light boron ions are used. High-performance NMOS devices with excellent SCE control designed for low-voltage digital, analog and RF operation were realized using this technique. For PMOS the use of TGi is restricted by significant diffusion of source/drain extensions due to the TGi damage induced TED.

A CMOS fully-integrated humidity sensor for a RFID sensor platform has been realized in 0.16µm CMOS technology. It consists of a top-metal finger capacitor, covered by a humidity-sensitive polyimide layer, and an energy-efficient inverter-based capacitance-to-digital converter (CDC). Measurements show that the CDC performs a 12.5-bit conversion in 0.8ms while consuming only 8.6µA from a 1.2V supply. Together with the co-integrated humidity sensor, this translates into a resolution of 0.05% RH in the range of 30% RH to 90% RH, at an energy consumption of only 8.3nJ per measurement.

A fully-integrated humidity sensor for a smart RFID sensor platform has been realized in 0.16μm standard CMOS technology. It consists of a top-metal finger-structure capacitor covered with a humidity-sensitive layer, combined with a micro-power flexible sensor interface based on a second-order incremental delta-sigma converter. The interface can be easily reconfigured to compensate for process variation of the sensing element. In a measurement time of 10.2 ms, the interface performs a 13-bits capacitance-to-digital conversion while consuming only 5.85 μA from 1.8 V supply. In combination with the co-integrated sensor capacitor, it thus provides a humidity-to-digital conversion with a resolution of 0.1% RH in the range of 20% to 90% RH at only 107 nJ per measurement. This represents a significant improvement in energy efficiency compared to existing capacitive-sensor interfaces with comparable performance.

This paper describes a precision temperature sensor based on dynamic threshold MOS (DTMOS) transistors. By using the DTMOS configuration, i.e. by connecting the body of a MOSFET to its gate, a near-ideal diode characteristic can be realized. The resulting device can then replace the substrate PNP used in most precision temperature sensors. After a two-temperature trim, the proposed sensor achieves an inaccuracy of ±0.1°C (3σ) over the military temperature range: −55°C to 125°C. This represents a 5× improvement in accuracy over previously reported MOSFET-based temperature sensors. The chip was implemented in a 0.16-μm standard CMOS process. At a conversion rate of 5Hz, it achieves a resolution of 33mK, while dissipating only 8.6 μW from a 1.8V supply.

A novel design and measuring results of an ultra-low power 12bit Successive-Approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optimised for the lowest power consumption. The proposed design has a power consumption of 0.52µW at a bitclock of 50-kHz and of 0.85µW at 100-kHz with a 1.2-V supply. The Figure-of-Merit reached with such implementation is of 66 fJ/conversion-step. The ADC was realised in the NXP CMOS 0.14µm technology with an area of 0.35 mm2. Only four metal layers were used in order to allow 3D integration of the sensors.

The design and first measuring results of an ultra-low power 12 bit successive-approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optmised for low power consumption. The power consumption is [email protected] from a 1.2V supply with a sample clock of 3.125kHz and [email protected] at 6.25kHz. This gives 136pJ per conversion or 66fJ per conversion step. As per authors' knowledge, 66fJ per conversion step is the best reported so far. The ADC was realised in the NXP CMOS [email protected] technology; the area was 0.35mm^2. Only four metal layers were used in order to allow 3D integration of the sensors.

Design strategies for power effective and high resolution Successive-Approximation ADCs for autonomous multi-sensor systems are discussed. Specifically, an optimisation for lowest possible power consumption of comparators is addressed and evaluated using both simulations and measurements of a fabricated Si test-chip. The proposed design solution is capable to provide a 12-bit resolution at 50-kHz with only 0.1uW power consumption on a 1.2-V supply. The achieved Figure-of-Merit is 165 ƒJ/convertion-step is, to our knowledge, the best ever reported. The complete ADC area is 0.35 mm2 in NXP 0.14um CMOS technology with only three metal layers.

Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p/sup +/ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge/sub 0.3/Si/sub 0.7/) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, /spl phi//sub B/, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q/sub bd/) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability.

High-performance poly-Sio,,Geo.3 gate PMOST and NMOST, compatible with conventional CMOS processing, are manufactured for devices with Le# down to 0.15pm. For PMOST we observe a -20% increase in saturation current and improved subthreshold slope from XlmV/dec to 75mV/dec wile off-state currents and short-channel effects are comparable to conventional devices. No influence of poly-Si,,Ge,, on the performance of NMOS transistors gates is observed. Introduction In deep submicron MOS transistors high substrate doping levels are needed to avoid short-channel effects and subthreshold leakage. This results in a decreased cader mobility and hence lower current drivability (ID?? of the devices. The situation can only be partly improved by changing channel profile ("super-steep retrograde" or"ground plane" channel designs) to reduce the channel dopant concentration. This cannot solve, however, the problem of high subthreshold currents due to low threshold voltage (VT). An alternative approach is based on the gate workfmction change. The change of the gate-to-semiconductor workfmction difference ACP,, allows one to reduce uniformly the surface channel doping while retaining the V, at the same level as for poly-Si gate. The resulting decrease in the effective transverse electric field towards the Si-SiO, interface as well as removal of the scattering centres from the channel leads to a higher carrier mobility and an increase of t h e I ~ ~ % Reduction in the channel doping level also improves the Ior/loff ratio since the subthreshold swing decreases with depletion layer capacitance. Additionally, the body-factor K goes down a property which can be utilised in low-voltage CMOS applications to prevent the threshold voltage variations with the substrate potential. Recently, polycrystalline silicon-germanium alloy (hereafter referred to as "poly-SiGe") has been suggested as a promising material for a singlep-type gate CMOS process [l] and has also been studied for deep submicron NMOST [2]. The poly-SiGe films are compatible with standard CMOS processing, they provide comparable nand better p-type dopants activation and, most importantly, an increase in Ge mole fraction induces a significant decrease in thep-type poly-SiGe workfunction [l]. However there have not been reported any results for deep submicron PMOS and NMOS devices. We present here a comparative study of deep submicron PMOST devices fabricated in a conventional way (with polySi gate) and with poly-Si,,,Ge,, as a gate material. We show that a substitution of poly-Si,,Ge,, for poly-Si leaves the main processing steps unchanged while it delivers a -20% increase in IDS~~ and improves the subthreshold slope S from 8lmVIdec to 75mV/dec with off-state currents and shortchannel effects at a comparable level. The body factorK decreases by more than 25% for submicron devices. At the Fig. 1 (a) Channel doping profiles used in this study as simulated by TMASUPREM-3; "default" As V, implant is 2.5~10'~@70keV, "V$"1 x 1012@70keV, " V$"0.7~10'~@50keV. (b) the effective transverse electric field towards the Si-SiO, interface as calculated on the basis of profiles in (a) with 1 .SV applied to ap-type gate. t Fig. 2 Flat-band voltage vs. tOx for poly-S&.,@e,, capacitors. AOMS is determined attox = 0. The thinnest gate oxide sample with poly-Si gate exhibit boron penetration which is not observed for poly-Si0,,Ge,, sample.

A CMOS process is developed in a research environment for integration studies of sub-50 nm MOSFETs with high-k (HiK) dielectrics, metal gates (MG), ultra-shallow junctions with laser thermal annealing (LTA), raised source/drain (RSD) and novel device architectures (e.g., double-gate transistors, strained channels). We have optimized the process parameters and show that high-performance transistors can be realized, promising direct applicability of the results to future manufacturing.

Electrical properties of MOS capacitors using MOCVD HfO/sub 2/ as gate dielectric have been investigated. A 900/spl deg/C 1s activation anneal of Ph-doped 680/spl deg/C-RTCVD demonstrated a good compatibility with high-k layers. The best MOS capacitor is obtained with EOT=1.93 nm and Jg = 1.6E-04 A/cm/sup 2/ at |V/sub FB/-1| which is > 2 orders of magnitude lower than SiO/sub 2/ with poly-Si gate. A minimal degradation of leakage current after 900/spl deg/C activation anneal and low effect of temperature dependence reveal the thermal stability of MOCVD HfO/sub 2/ gate stack. Nevertheless, upon 1000/spl deg/C activation anneal only the LPCVD poly resulted in working MOS capacitor. The found leakage current was > 2 order of magnitude higher compared to a 900/spl deg/C activation anneal.

We have studied an aggressive lateral MOS channel profiling combined with gate work function engineering for sub-0.13 /spl mu/m generation PMOSFETs oriented for low-voltage operation. In this scheme, the Ge fraction in the poly-SiGe gate was used to control threshold voltage V/sub T/, while short channel effects (SCE) were completely suppressed down to 100 nm gate lengths by heavily doped, sharp envelopes around the source/drain. The fabricated bulk devices exhibit low DIBL, no V/sub T/ roll-off behaviour, and 67 mV/dec sub-V/sub T/ voltage swing. The low channel doping leads to significant improvements in the channel mobility and parasitic capacitances, resulting in excellent I/sub on//I/sub off/ behaviour and record ring oscillator delays for low-voltage operation. Process variation analysis confirmed the high manufacturing potential for the approach suggested. The approach can be extended to n-type devices with a suitable choice of gate work function.

Front-end optimization of a 0.15 /spl mu/m CMOS technology is described demonstrating the feasibility of a Through-the-Gate implantation (TGi) concept for super-steep retrograde well formation. In this paper we show for the first time that excellent transistor matching of NMOS devices with TGi processing is obtained. It demonstrates the absence of any anomalies due to stochastic effects associated with this novel approach for boron super-steep retrograde well formation and excellent 0.15 /spl mu/m CMOS transistor and circuit performance was obtained.

We show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18 /spl mu/m devices are manufactured using p- and n-type poly-Si/Si/sub 0.8/Ge/sub 0.2/ gates.

This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenario's for CMOS technologies lead to strong degradation of analog transistor performance. As a result the combined optimization of digital and analog devices for system-on-a-chip applications will require increasingly elaborate process modifications. New device solutions such as metal gate integration and asymmetric (source-side-only) workfunction modification offer process options for future mixed-signal CMOS applications.

The limits of scaling of planar Si MOSFET devices has been a subject of increasing interest in recent years. Consumer demand for high-performance electronic products has stimulated an ever-increasing rate of scaling of mainstream CMOS. Several results for devices with sub-50 nm gate lengths have already been reported (e.g. Timp et al., 1998; Chau et al., 2000; Wakabayashi et al., 2000) to approach the required performance values. We present here the results of study of manufacturability of sub-50 nm MOSFETs using tools routinely available for production of the 0.18 /spl mu/m CMOS generation. We show that by adapting 248 nm lithography, using nonequilibrium n-type junction formation and specially developed low-temperature processing, it is possible to manufacture devices with gate lengths as small as 15 nm. It is also confirmed that heavily pocketed devices with sub-50 nm gates show deterioration in performance.

In this paper we study the integration of Boron ultra-shallow junctions (USJ) obtained by Germanium pre-amorphization, Fluorine co-implantation and fast ramp-up and ramp-down anneals into advanced p-channel metal-oxide-semiconductor (PMOS) devices. Several integration issues associated to these USJ are investigated: short-channel effects control, implantation tilt angle influence, junction de-activation, thermal budget, silicide process. We show that remarkable PMOS device performance enhancement (I on=450 µA/µm at I off=250 nA/µm for devices with L g\cong50 nm) can be achieved when full potential of highly-active and abrupt USJ is exploited by combining it with a low thermal budget integration scheme and a low contact resistance NiSi.

The thermal and electrical stability of HfO 2 -HfSiO 4 dielectric layers with polysilicon electrodes are investigated in view of their use as gate dielectrics in advanced complementary metal oxide semiconductor (CMOS) technologies. The layers were deposited on 1 nm silicon oxide layers using metallorganic chemical vapor deposition (MOCVD). In situ p-doped polysilicon electrodes were deposited using rapid thermal chemical vapor deposition and low pressure chemical vapor deposition, respectively. The influence of rapid thermal annealing and postdeposition annealing of the high-k layers was investigated using MOS capacitors. The lowest equivalent oxide thickness was around 19.3 A with a leakage current reduction of approximately 1000 times as compared to SiO 2 . MOSFETs fabricated using a standard direct gate etch approach were used to study the stability of the dielectric and device properties as functions of activation anneal and implant conditions. A major problem was found to be the stability of the threshold voltage V T . After 50 consecutive I d -V g dc sweeps from -1 to +2 V, the threshold voltage of n-MOS devices shifted 50-200 mV. Using pulsed I d -V g measurement technique, a hysteresis on the order of 300-400 mV was found. Only a minor improvement was achieved by different annealing of the layers. In conclusion, it was found that these layers exhibit unacceptably high instability to provide a solution as a gate dielectric for advanced CMOS technologies.