CMOS device optimization for mixed-signal technologies

This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenario's for CMOS technologies lead to strong degradation of analog transistor performance. As a result the combined optimization of digital and analog devices for system-on-a-chip applications will require increasingly elaborate process modifications. New device solutions such as metal gate integration and asymmetric (source-side-only) workfunction modification offer process options for future mixed-signal CMOS applications.