Search

This paper presents design challenges and solutions for the fifth generation (5G) phased-array transceiver ICs in millimeter-wave (MMW) frequency bands. A 28nm bulk CMOS device technology is selected to integrate multiple RF phased-array elements in a single-chip to achieve a high-level of TX EIRP and RX sensitivity. Several design approaches of gain, P OUT , stability, reliability and linearity enhancement techniques are applied to enable CMOS as a key device solution for 5G applications in MMW frequency bands. A 39GHz band 16-channel CMOS RF phased-array transceiver IC is designed and can support 4T/4R MIMO base-station applications including ×64 RF phased-array ICs (total 1,024 phased-array elements). T/RX paths have gain dynamic ranges of >30/40dB for flexibility and scalability. The TX path shows P OUT /Ch. of >6.0dBm at EVM of -34dB (800MHz) and P DC /Ch. of 105mW. The RX path performs NF of 4.2dB, EVM of -38dB (100MHz) and P DC /Ch. of 39mW. These state-of-the-art results lead to TX EIRP of >55dBm and RX sensitivity of

As BEOL pitch continues to aggressively scale, contributions from pattern dimension and edge placement constrict the available geometry of interconnects. In particular, the critical minimum insulator spacing which defines a technologies max operating voltage is now limited by Vx to Mx spacing. This spacing has historically been a challenge since the introduction of self-aligned vias due to the loss of CD and chamfer control in the non-self-aligned direction. As pitch continued to shrink from self-aligned via introduction around the 22 nm node, the fraction of via CD control and edge placement compared to the dielectric spacing between interconnects has continued to grow. Alone this trend could be combated by increasing the dielectric spacing, however, the exponential increase in Cu resistivity (under scaling) has forced BEOL technologies into strong line/space asymmetry to keep line resistance under control. At pitches below 32 nm these factors reach a tipping point, either design to exponentially increasing line resistance or lower the technology Vmax. Both approaches cause performance degradation to achieve pitch scaling

A fully aligned via (FAV) integration scheme is introduced and demonstrated at 36 nm metal pitch, with extendibility to beyond the 7 nm node. Selective chemistries were developed to recess Cu and W wires and their associated barrier liner materials, so as to create local topography with no adverse effects on these wiring levels or their dielectrics. Dielectric cap layers were optimized for excellent via RIE selectivity, to act as via guiding structures during subsequent level pattern definition. This combination mitigates via overlay and critical dimension (CD) errors. FAV integration can enable line/via area scaling for 70% lower line resistances and 30% larger via contact areas at the same node. Concurrently, FAV improves TDDB reliability through increased minimum insulator spacing, and EM reliability by maximizing via/wire contact area.

We have developed an integration technology for the single electron transistor (SET)/CMOS hybrid systems. SET and CMOS transistors can be optimized without any possible degradation due to mixing dissimilar devices by adopting just one extra mask step for the separate gate oxidation (SGOX). We have confirmed that discrete devices show ideal characteristics required for the SET/CMOS hybrid systems. An SET shows obvious Coulomb oscillations with a 200-mV period and CMOS transistors show high voltage gain. Based on the hybrid process, new hybrid circuits, called periodic multiband filters, are proposed and successfully implemented. The new filter is designed to perform a filtering operation according to the periodic multiple blocking bands of which a period is originated from the SET. Such a novel function was implemented efficiently with a few transistors by making full use of the periodic nature of SET characteristics.

Deuterium annealing has been widely demonstrated to be an effective way to improve the hot-carrier reliability of MOS devices. In this paper, we present a thorough study of the effect of deuterium pressure on the characteristics and hot-carrier reliability of MOS devices. N-channel submicron MOS transistors were annealed in deuterium with various pressures, temperatures and annealing times. It is found that device reliability initially improves as deuterium pressure is increased. It reaches a maximum and then begins to degrade with further increase of pressure. For the devices after hydrogen anneal, device reliability constantly degrades as the hydrogen pressure increases. It is concluded that the benefit of high pressure deuterium processing on device reliability is attributed to improved deuterium incorporation, while annealing-induced interface trap creation can negate the benefit at extreme high pressure. It is further shown that the processing temperature can be lowered with high pressure while still maintaining the deuteration benefit. This is particularly significant for future CMOS technology that requires a reduced thermal budget.

Nitrogen implantation on the silicon substrate was performed before the gate oxidation at a fixed energy of 30 keV and with the split dose of 1.0/spl times/10/sup 14//cm/sup 2/ and 2.0/spl times/10/sup 14//cm/sup 2/. Initial O/sub 2/ injection method was applied for gate oxidation. The method is composed of an O/sub 2/ injection/N/sub 2/ anneal/main oxidation, and the control process is composed of a N/sub 2/ anneal/main oxidation. CMOS transistors with gate oxide thickness of 2 nm and channel length of 0.13 /spl mu/m have been fabricated by use of the method. Compared to the control process, the initial O/sub 2/ injection process increases the amount of nitrogen piled up at the Si/SiO/sub 2/ interface and suppresses the growth of gate oxide effectively. Using this method, the oxidation retarding effect of nitrogen was enhanced. Driving currents, hot carrier reliability, and time-zero dielectric breakdown (TZDB) characteristics were improved.

Several body contact arrangement types have been studied to improve the parasitic phenomena such as the edge transistor effect and the bipolar action. The H-gate SOI MOSFET with the body contacts at both ends of channel was found to be most effective to suppress the edge transistor effect and reduce the drain leakage current and the bipolar action.

HfO2 thin films were deposited on SiNx-passivated Si wafers at 300 and 400 °C using an atomic-layer-deposition technique. The SiNx films were deposited by another atomic-layer-deposition process at 595 °C. The SiNx films worked well as barriers to both Si and O diffusion, resulting in a small decrease in the capacitance density even after post-annealing at temperatures up to 1000 °C, compared either to the HfO2 film deposited directly on Si or an Al2O3-barrier-layer/Si substrate. The decrease in the capacitance density after post-annealing, although relatively small, was due to Hf and O diffusion into the interface layer. Interestingly, post-annealing under an atmosphere containing small amount of oxygen (∼1%) decreased the capacitance density to a smaller degree. However, the interface and bulk capturing of the carrier was serious, resulting in a rather large hysteresis (∼100 mV) voltage in the capacitance–voltage measurements even after post-annealing.

A first multilevel vertical-channel silicon-oxide-nitride-oxide-silicon (MLVC-SONOS) memory cell is proposed and fabricated using 0.12-μm silicon-on-insulator (SOI) standard logic process for Flash memory cell with ultrahigh density. If NAND array structure is used, the unit cell size of MLVC-SONOS is 4F2. Further reduction of cell size is possible by using the multilevel concept which is originated from the steady states by two carrier transports from both the substrate and the gate. The program threshold voltages and their windows are uniform and controllable depending on the negative gate bias conditions. In addition, we propose a new endurance measurement method for multilevels and report the retention characteristics for multilevel memory operation.

The effect of deuterium on hot-carrier reliability of fully processed 0.18 /spl mu/m silicon-on-insulator (SOI) devices is investigated. The improvement of device lifetime by a factor of 30 is achieved by passivating the interface defects with deuterium instead of hydrogen. The hydrogen/deuterium isotope effect (/spl gamma/), defined as the ratio of generation interface traps of a hydrogenated device to that of a deuterated one, shows strong dependence on the gate stress voltages (V/sub gs/). Increasing V/sub gs/ results in the decrease of /spl gamma/. These results suggest that the breaking of Si-H(D) bonds by channel electrons through the vibrational heating mechanism may play an important role in the degradation of deep submicron SOI devices.

Microwave plasma chemical vapor deposition (MPCVD) was employed to synthesize high quality centimeter scale graphene film at low temperatures. Monolayer graphene was obtained by varying the gas mixing ratio of hydrogen and methane to 80:1. Using advantages of MPCVD, the synthesis temperature was decreased from 750 °C down to 450 °C. Optical microscopy and Raman mapping images exhibited that a large area monolayer graphene was synthesized regardless of the temperatures. Since the overall transparency of 89% and low sheet resistances ranging from 590 to 1855 Ω/sq of graphene films were achieved at considerably low synthesis temperatures, MPCVD can be adopted in manufacturing future large-area electronic devices based on graphene film.

By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V/sub gs/ stress, HEIP is found to dominate the shift of threshold voltage V/sub t/. When V/sub gs/ increases to a moderate value, the V/sub t/ shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V/sub gs/ is increased further to V/sub gs/=V/sub ds/. For the first time, the effects of interface trap creation and oxide charge trapping on the V/sub t/ shift are quantified by the proposed technique.

We present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO/sub 2//Si interface. We have achieved a significant lifetime improvement (90/spl times/) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization.

The giant deuterium isotope effect found previously for NMOS hot electron degradation is applied to study defect generation at the Si-SiO/sub 2/ interface. The data suggest that interface defects related to hydrogen depassivation may be generated directly by channel hot electrons bombarding the interface without the necessity of injection into the oxide. This is in contrast to the standard teaching that energetic holes, created by impact ionization, and injected into the oxide are the main cause for hydrogen-related defect generation at the Si-SiO/sub 2/ interfaces.

This work presents the design and fabrication of the LC voltage-controlled oscillator (VCO) using 1-poly 3-metal CMOS process aimed for use in current memory manufacturing process. Poor characteristics of highly-resistive and immune to substrate-coupling metal-3 inductor in LC resonator were overcome by dual metal structure and patterned-ground shield (PGS) strategy. Fabricated VCO operated from 2.48 GHz to 2.73 GHz tuned by accumulation-mode MOS varactor. The corresponding tuning range was 250 MHz. The measured phase noise was - 113.5 dBc/Hz at 1 MHz offset at 2.48 GHz carrier frequency. The current consumption and corresponding power consumption were about 1.04 mA and 1.87 mW respectively.

Variation of DRAM retention time induced by thermal stress was investigated. Thermal activation energies (Ea) of sub-threshold leakage, junction leakage and GIDL (Gate Induced Drain Leakage) current of a DRAM cell were measured using the test vehicles. The values were compared with Ea of 1/tREF for the DRAM cell of which the retention time had been varied after a thermal stress. Ea of 1/tREF for the thermally degraded DRAM cell was in the range of that for GIDL current, while Ea for the normal DRAM cells with high retention time was in the range of Ea for junction leakage. It is insisted that the thermal degradation of retention time is induced by increase in GIDL current. The contributions of gate oxide/substrate interface states to the GIDL current are discussed.

The atomic layer deposition technique has been applied to the growth of Al2O3 thin films on the substrates of Si(100), 100-nm-thick SiO2 covered Si(100) [SiO2/Si(100)], and 90-nm-thick TiN covered SiO2/Si(100). The growth rate of Al2O3 films was 0.19 nm/cycle and identical for all substrates employed under the surface controlled process. However, the optical properties of Al2O3 films were significantly affected by different substrates. The average interband-oscillator energy and refractive index parameter were determined to be 3.330 eV and 2.992×10−14 eV m2 for Al2O3 film grown on Si(100), while those for the film grown on SiO2/Si(100) were 4.492 eV and 2.074×10−14 eV m2, respectively.

Negative bias temperature instability (NBTI) in triple gate transistors was investigated for the first time. It is found that the threshold voltage shift caused by negative bias temperature stress in conventional configuration of triple gate transistors is worse than that in planar transistors. This is due to the larger trap state density of the [110] side surface of the active silicon and it is verified by comparing two types of triple gate transistors each of which has [110] side surface and (100) side surface. The -direction channel is proposed as one of the structural options to reduce the degradation of NBTI in triple gate transistors.

Fully working 1.25 /spl mu/m/sup 2/ 6T SRAM cell with 45 nm Triple Gate transistors having excellent short-channel characteristics is demonstrated by using a planar layout of 90 nm CMOS technology. This result represents the first experimental demonstration of a fully working Triple Gate SRAM cell with the smallest cell size ever reported.

Integration of MIM capacitors into 90 nm mixed-signal applications is demonstrated for the first time with the testing vehicle of AD converter using low-k (k=2.7) Cu dual damascene process. To obtain high resolution MIM capacitor, process such as electrode etching and CMP of upper Cu line was carefully optimized. The optimized process condition yields more reliable MIM capacitors with less parasitic components. The parasitic capacitance caused by surrounding upper metal interconnect gives significant effect for IMD thickness less than 300 nm. For parasitic capacitance-free MIM capacitor, a landing-metal type is suggested, and parasitic capacitance is reduced more than 60% compared with conventional capacitor structure.

Double raised source/drain (DR) ultra thin film (UTF) SOI CMOSFETs were experimented for the first time. Double Si selective epitaxial growth (SEG) process before source/drain extension and deep source/drain implant is greatly recommended for excellent device performance with a reduced series resistance. Fully depleted (FD) SOI devices with 50 nm gate length for embedded SRAM technology were investigated for different SOI film thickness. Transistor performances of 700 /spl mu/A//spl mu/m and 355 /spl mu/A//spl mu/m at 1.0 V operation and Ioff = 90 nA//spl mu/m was obtained for NMOS and PMOS devices, respectively. Drain induced barrier lowering (DIBL) was improved as the SOI film thickness was scaled down to 17 nm from 50 nm. The static noise margin (SNM) for a 1.1 /spl mu/m/sup 2/ SRAM cell was 210 mV and ring oscillator speed was improved by 24% compared to bulk devices.

Ultra low power CMOS 6T-SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric were successfully demonstrated (bit-cell size=2.14 /spl mu/m/sup 2/). Equivalent oxide thickness (EOT) of 1.56 nm, the thin high-k gate dielectric NMOS and PMOS transistor had 470 and 150 /spl mu/A//spl mu/m at Ioff=0.1 nA//spl mu/m and Vdd=1.2 V, respectively. By deliberate optimizing the conditions of post nitridation and post deposition annealing (PDA) such as O/sub 2/ and N/sub 2/ PDA temperature, 60 and 82% of NMOS and PMOS mobility, respectively, compared to those of oxynitride were achieved without increasing EOT. And also, reliabilities of TDDB and HCI, and flicker noise characteristics of the thin high-k transistors were improved. For the 6T-SRAM with optimized thin high-k gate dielectric, static noise margin (SNM), cell delay, and chip yield were comparable to those of the oxynitride device while dynamic power was more than 2 orders lower (Vdd=1.0/spl sim/1.2 V).

Ultra low power 1.10 /spl mu/m/sup 2/ 6T-SRAM chip with HfO/sub 2/-Al/sub 2/O/sub 3/ gate dielectric was for the first time successfully demonstrated for the system-on-chip applications. By carefully optimizing gate pre-doping process, gate leakage current was dramatically suppressed and poly deletion was reduced. Device performance was improved by 15% and 12% for NFET and PFET, respectively. The threshold voltage of long channel transistor was well controlled to the acceptable value (0.4V) by channel engineering. Equivalent oxide thickness of HfO/sub 2/-Al/sub 2/O/sub 3/ film was 17/spl Aring/ and gate leakage current density was 1600-times lower than that of the oxynitride. Current performance of 90nm gate length NFET and PFET with HfO/sub 2/-Al/sub 2/O/sub 3/ were 335 and 115 /spl mu/A/ /spl mu/m, while Ioff were 0.9 and 2.0pA/ /spl mu/m, respectively. SNM value of 1.10 /spl mu/m/sup 2/ 6T-SRAM bit cell was 340mV at Vdd = 1.2V. Stand-by current of the SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/ was decreased by 2 orders, while access time was 1.65 times larger compared with that of SRAM chips with oxynitride at Vdd = 1.2V.

Relationship between mechanical stress engineering and flicker noise are clarified for the first time using a 50nm level CMOS technology. It is found that enhanced mechanical stress degrades flicker noise characteristics. Trap states and dipoles generated by the stress are considered to be the cause of degradation. The transistor performance enhancement with flicker noise reduction by nitrogen profile optimization in gate dielectric is demonstrated as a countermeasure.

For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO/sub 2/-Al/sub 2/O/sub 3/ laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1 mA/cm/sup 2/ at V/sub g/=+1.0 V) and low EOT (15.6 /spl Aring/) sufficiently satisfy the specifications (EOT=12/spl sim/20 /spl Aring/, J/sub g/=2.2 mA/cm/sup 2/) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2 V V/sub dd/ are 585 /spl mu//spl Aring///spl mu/m (I/sub off/= 10 nA//spl mu/m) for nMOSFET and 265 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET, which are approximately 80% of those of nitrided SiO/sub 2/. In terms of I/sub on/-I/sub off/ characteristics of n/pMOSFETs, these results represent the best current performance compared with previous reports for poly-Si gate CMOSFETs with high-k gate dielectrics.

Manufacturable embedded CMOS 6T-SRAM with the HfO/sub 2/-Al/sub 2/O/sub 3/ dielectric for system-on-chip (SoC) applications is successfully demonstrated for the first time in the semiconductor industry. The possibility of the high-k gate dielectric in low power SoC applications is suggested. 0.11/spl mu/m NFET and PFET devices with thin high-k gate dielectric have 470 and 150/spl mu/A//spl mu/m at Ioff=0.1nA/um and Vdd=1.2V, respectively. Inversion thickness of NFET and PFET are 2.4nm and 2.7nm, respectively. Gate leakage current of the high-k is 1000 times lower than that of the oxynitride at the accumulation region. Static noise margin of 2.14/spl mu/m/sup 2/ 6T-SRAM bit cell is about 300mV at Vdd=1.2V. 6T-SRAM chip yield of the high-k is comparable to that of the oxynitride. The post nitridation after high-k film deposition is very important to the yield of the SRAM chips due to the suppression of the PFET boron penetration. Stand-by current of the SRAM chips with the high-k is shown to be a decreases of 60% compared with the oxynitride.

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.

A highly manufacturable and high performance 0.13 /spl mu/m CMOS process for a 1.5 V microprocessor is proposed. The device is integrated by dual-doped poly-Si transistors with STI, additionally doped gate poly, highly doped drain extension and Co-salicide structure. Co-salicide gate with sheet resistance below 5 ohm/sq. in the 0.1 /spl mu/m -length gate line is obtained. By using indium and boron as channel implants, and employing n/sup +/poly gates for nMOS while low-energy boron instead of BF2 is used for pMOS gates, the Idsat values of 770 /spl mu/A//spl mu/m and 31 /spl mu/A//spl mu/m have been achieved with the electrical gate oxide thickness of 2.6 nm and 2.8 nm for nMOS and pMOS, respectively.

We developed a new systematic calibration procedure which was applied to the calibration of the diffusivity, segregation and TED model of the indium impurity. The TED of the indium impurity has been studied using 4 different groups of experimental conditions. Although the indium is susceptible to the TED, the RTA is effective to suppress the TED effect and maintain a steep retrograde profile. Like the boron, the indium shows significant oxidation-enhanced diffusion in silicon and has segregation coefficients at the Si/SiO/sub 2/ interface much less than 1. In contrast, however, the segregation coefficient of indium decreases as the temperature increases. The accuracy of the proposed technique is validated by SIMS data and 0.15-/spl mu/m device characteristics such as Vth and Idsat with errors less than 5% between simulation and experiment.

The characteristics of 20 /spl Aring/ gate oxide formed by an RTO (Rapid Thermal Oxidation) process with an NO+O/sub 2/ mixture ambient have been investigated. Due to the high nitrogen concentration in the oxide, good boron penetration suppression and higher interface trap density were observed. The low thermal cycle of the RTO process facilitated the formation of SSR (Super Steep Retrograde) channel and reduced RSCE (Reverse Short Channel Effect). The transistor performance was Idsat n/p=925/370 /spl mu/A//spl mu/m for Vdd=1.5 V and Idoff n/p=10 nA//spl mu/m. The TDDB and hot carrier characteristics were evaluated and found to be satisfactory.

Thin-film silicon-on-insulator (TFSOI) MOSFET has emerged as a strong candidate for high performance, high density and latch-up free CMOS devices with less fabrication steps. Thin silicon film should be used to achieve good behavior in SOI MOSFET. However, most of the papers on TFSOI have reported high parasitic source/drain series resistance and contact resistance, which tends to obscure the performance advantages of SOI. In this paper, we examined effects of top silicon film thickness (Tsi) on contact series resistance and contact hole etching method.

A high performance and cost-effective process for a 0.5 /spl mu/m CMOS logic device optimized for 3.3 V has been developed. To fill contacts and via holes, an in-situ Al reflow technique was employed instead of the high cost W-plug process. It was found that the in-situ Al reflow technique was very effective in improving the electrical properties and reliabilities of the multilevel interconnects. Quasi-global inter-metal-dielectric (IMD) planarization has been achieved by the COmbining PHOtoresist etchback and SOG etchback (COPHOS) process.

High performance microprocessors with high stabilities are fabricated on Si and SiGe inserted (SGI) SOI wafers. The operation margins of voltages and frequency are characterized. For body floating devices, the operation margins at high Vdd and low frequency are narrow due to the floating body effect (FBE). These operation limits are drastically improved by applying a body contact for only NMOS at the critical circuits sensitive to the FBE. The maximum operation voltage increases from 1.8 V up to 2.5 V. The minimum operation frequency is lowered from 370 MHz to 220 MHz. The functionality of the NMOS body contact SOI microprocessor is comparable to that of the bulk. To maximize the SOI performance gain, body contacted and floating SOI devices should be optimized, and the smaller portion of body contacted devices are conclusive. For body floating SOI devices, the SGI SOI technology is very effective in suppressing SOI FBE and provides stable circuit operation.

Temperature profiles of surface mount components progressing through convection and infrared reflow systems are studied with respect to package size, inter-component spacing, and loading density. For constant forcing temperature, T/sub max/ varies inversely with component mass. A minimum component spacing required to minimize T/sub max/ variation is established. Package delamination and cracking are shown to depend primarily on T/sub max/.

Microstructure changes, after annealing, of tungsten suicide (WSi ϰ ) films formed on the polysilicon films by CVD (chemical vapor deposition) and by sputtering were compared. For both CVD and sputtered WSi ϰ films, microstructural evolutions during annealing were caused by three mechanisms; crystallization from amorphous phase, stoichiometrical change, and grain growth. The microstructures and the electrical resistances of WSi ϰ films after annealing were depended on the deposition method. The movement of excess Si in WSi ϰ film to poly-silicon during annealing was faster in case of sputtering than in case of CVD. At annealing temperature below 850°C, CVD films showed higher resistivity and smaller grain size than sputtered films. On the other hand, at anneal temperature above 850°C, the grain growth rate of the CVD film was higher than that of the sputtered film, and the CVD film resulted in lower resistivity than the sputtered film. The retardation of grain growth for the sputter-WSi ϰ film is thought to be caused by impurity contamination such as argon added into the film during sputtering.

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

Fully depleted silicon-on-insulator (FD SOI) devices with 70 nm gate lengths for embedded static random access memory (SRAM) technology were investigated for different SOI film thickness. Transistor performances of 700 µA/µm and 320 µA/µm were obtained for n-type and p-type metal-oxide semiconductor field effect transistor (NMOSFET and PMOSFET) devices, respectively at 1.0 V operation voltage and I off=75 nA/µm. Si selective epitaxial growth (SEG) process was well optimized. Both the single raised (SR) and double raised (DR) source/drain process were studied to reduce parasitic series resistance. For the DR process, both NMOSFET and PMOSFET performance are improved by 9 and 13% respectively, compared to the SR process. Drain induced barrier lowering (DIBL) was improved from 100 mV to 13 mV as the SOI film thickness was scaled down from 50 nm to 17 nm. Due to the self-heating effect, the AC current is 15% higher than the DC current for the case of 40 nm SOI thickness. The static noise margin (SNM) for a 1.1 µm2 6T-SRAM cell was 210 mV and ring oscillator speed was improved by 24% compared to bulk devices.