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Continuous scaling of device dimension pushed Si channel to its physical limit, alternative high mobility channels such as (Si)Ge and (In)GaAs have been considered to replace Si to further enhance CMOS performance. In the meantime, ultrathin body (UTB) semiconductor-on-insulator is compulsory structure for improved gate control and immunity against short channel effects in the ultimately scaled high performance and low power dissipation CMOS. To realize stacked multi- channel semiconductor-on-insulator platform on current mainstream Si wafers, layer transfer technology [1-3] utilizing direct bonding and selective etching was developed to integrate (Si)Ge or (In)GaAs channels on Si, showing great potential for ultimate device structures with heterogeneous integration. Figure 1(a) is the process flow for integrating InGaAs channel onto SiGe-on-insulator (SGOI) structure utilizing layer transfer technology [4]. It started with bottom SGOI pMOSFET fabrication. The SGOI structure was realized by 2-step Ge condensation technique, resulting in Ge content of 70%. After high k metal gate process, self-aligned Ni-SiGe alloy was formed as S/D metal. Subsequently, SiO2 interlayer was deposited by CVD, followed by CMP planarization. Then, InGaAs grown on InP was directly bonded onto SiO2 and InP substrates were selectively etched away. Finally, the top InGaAsOI nMOSFET fabrication and metal interconnection completed the CMOS fabrication. Fig. 1(b) shows the cross-sectional TEM images of fabricated InGaAs/SiGe channel stacked CMOS. Well aligned top and bottom devices are seen without any distinct defects. Figures 2 is a schematic flow for fabricating Ge/Si double channel-on-insulator structure by low temperature hetero-layer bonding technology (LT-HBT). The technology starts with the preparation of donor wafers (Fig. 2(a)) for the top Ge channel layer and host wafers (Fig. 2(b)) for the bottom Si channel layer. For donor wafers, a 200-nm-thick Ge was epitaxially grown on SOI wafer by reduced pressure CVD. After CMP planarization, ALD SiO2 is deposited onto Ge. For host wafers, implantation and dopant activation were carried out, followed by chemical treatment for Si oxidation. After surface activation by room temperature chemical treatment (Fig. 2(c)), the direct wafer bonding of both SiO2 surface was performed at 200 °C in a press machine (Fig. 2(d)). Then, the Si substrate of the donor wafer was removed with deep RIE. At this time, the BOX layer of the donor wafer serves as an etch-stop layer. Subsequently, the BOX layer and thin Si layer of the donor wafer were removed selectively in HF and TMAH solution, respectively (Fig. 2(f)). To precise control the top Ge channel thickness, a series of low damage etching process was adapted to thin down Ge (Fig. 2(g)). The realized double channel structure is fully isolated with an insulating insertion layer,[5] which is very promising for realizing novel complementary FET (CFET) with minimum process steps. The cross-sectional TEM image of Ge/Si stacked channel of CFET after high k metal gate process is demonstrated in Fig. 2(h). Even more multiple stacks can be realized by using LT-HBT. A vertically stacked three-layer structure with 2 bottom Si layers and 1 top Ge layers is also demonstrated using SOI-based donor wafers in Fig. 3, indicating the highly integrated density channel structure is possible. The feasibility of layer transfer technology has been proved for multi-channel structure with high mobility channels for N2 node and beyond. Acknowledgement This work was supported by JST Japan-Taiwan Collaborative Research Program, Grant Number JPMJKB1902, Japan and the Ministry of Science and Technology under Grant Number MOST-109-2628-E-492-001-MY3, 109-2923-E-492-001-MY3, 107-2221-E-492-016-MY3. References [1] T. Maeda et al., Appl. Phys. Lett. 109, 262104 (2016). [2] W. H. Chang et al., Mater. Sci. Semicond. Process 70, 123 (2017). [3]W. H. Chang et al., IEEE Trans. Electron Device 64, 4615 (2017). [4] T. Irisawa et al., VLSI 146 (2014). [5] T. Z. Hong et al., IEDM (2020) Figure 1

In this paper, we achieved excellent variation control, endurance enhancement, and leakage reduction in zirconium (Zr)-doped hafnium oxide (Hf1–xZrxO2) based ferroelectric films by the germination ...

Monolayer doping is a possible method for achieving complex-geometry structures with different semiconductors. Understanding the dopant diffusion behavior of monolayer doping, especially under different heating sources, is essential for further improvement. We examine and compare the doping profile and dopant activation with two different heating sources (rapid thermal annealing and microwave annealing), especially focused on SiO2/Si interface. These heating sources are used for junction diode fabrication, to realize current switching behavior. Direct observations of monolayer doping profiles, especially inside the capping oxide, are discussed to provide quantitative information for dopant concentration. This can provide significant information for better tuning of surface chemistries and process protocols applied in monolayer doping methodologies.

The lack of effective synthesis techniques for achieving wafer-scale uniformity and high crystallinity remains one of the major obstacles for two-dimensional (2D) layered materials in practical applications. 2D solid-phase crystallization (2DSPC) is proposed based on the area-scalable and semiconductor-process-compatible sputtering and thermal annealing techniques. It successfully synthesizes few-layer 2H-MoTe2 with a monocrystalline grain size exceeding half a centimeter on an amorphous substrate of silicon dioxide. The extremely large grain size is made possible through a two-step annealing process in an inert atmosphere. The initial rapid thermal annealing at high temperatures produces hexagonal monocrystalline 2H-MoTe2 seeds with low density and the subsequent long-duration furnace annealing at low temperatures enlarges the monocrystalline domains only from the pre-existing seeds. The 2DSPC mechanism and its morphological evolution agree with the classical nucleation theory and kinetic Wulff construction theory, respectively. Our result suggests the promising potential of 2DSPC as a simple yet effective route for synthesizing future wafer-scale, high-quality 2D materials.

We investigated a high electron mobility Ge FinFET fabricated by defect-free and roughness-free atomic layer neutral beam etching (NBE) compared with one fabricated by conventional plasma etching (PE). The etching interface roughness and defect were estimated by high-resolution transmission electron microscopy (TEM). In the case of using atomic layer defect-free NBE, the root-mean-square roughness of the Ge Fin sidewall surface is 1/3 times smaller than that using PE. Then, the electron mobility of Ge FinFET was improved by 1.65 times compared with that of a PE etched FinFET sample. For the subthreshold swing, the defect density of the interface between the Ge and gate dielectric film was improved by NBE. Ioff average currents of NBE and PE were around 18.1 and 57.6 nA/μm, respectively. As a result, NBE reduces the off-leakage current to 1/3 times less than PE. This corresponded to the differences in surface roughness and defect generation between NBE and PE. Therefore, we found that NBE could achieve a good performance by defect-free and atomically-flat etching the surface.

The phonon transport in the lateral direction for gap-controlled Si nanopillar/SiGe interlayer composite materials was investigated to eliminate heat generation in the channel area for advanced MOS transistors. The gap-controlled Si NP/SiGe composite layer showed 1/100 times lower thermal conductivity than Si bulk. Then, the phonon transport behavior in lateral direction could be predicted by the combination between 3-omega measurement method for thermal conductivity and Landauer approach for phonon transport in Si NP/Si0.7Ge0.3 interlayer composite structure. We found that the NP structure could regulate the phonon transport in the lateral direction by changing the NP gaps. As such, this structure achieves the first step toward phonon transport management in the same electron transportation direction of planar-type MOSFETs and represents a promising solution to heat generation for advanced CMOS devices.

In this work, the ferroelectric thin-film transistor (Fe-TFT) with polycrystalline-silicon (poly-Si) channel and HfZrO x gate dielectric is fabricated to study the characteristics of non-volatile memory (NVM). Significant threshold voltage (V TH) modulation can be achieved with low pulse voltages less than ±3.5 V and pulse widths within 1 μs. In order to achieve the NVM characteristics of low voltage and high speed operation, the impact of the program/erase (PRG/ERS) pulse voltage (V PRG/V ERS) and pulse width on endurance is a critical consideration. In the study of the pulse width effect on endurance, it can be observed that the V TH in PRG-state exhibits the wake-up effect at both short and long pulse widths. In addition, with the increase of pulse width, the V TH in the PRG-state exhibits significant fatigue effect and subthreshold swing (SS) degradation effect. For V TH in the ERS-state, the increase of the pulse width also exhibits the fatigue effect and the SS degradation effect, which is dominated by the SS degradation effect at long pulse widths. In the study of the pulse voltage effect on endurance, the increase of V PRG shows the imprint effect that the V TH in either PRG- or ERS-state reveals a decreasing trend. When the V ERS increases, the SS of the PRG- and ERS-states is degraded, and the fatigue effect of the PRG-state is enhanced. Moreover, the retention characteristics of poly-Si Fe-TFTs exhibit stable characteristics at both room temperature and 50 °C.

Microwave annealing (MWA) processes were used for the first time to obtain Ti supersaturated Si. High Ti doses were ion implanted on Si substrates and subsequently MWA processed to recrystallize the amorphous layer. The resulting layers were monocrystalline with a high density of defects. Ti depth profiles indicate that diffusion is avoided once recrystallization is produced. Finally, the electronic transport properties measurements point to a decoupling effect between the Si:Ti layer and the substrate. The implanted layer present also a shallow donor and very high Hall mobility.

According to quantum transport simulations, source-to-drain tunneling (SDT) has been recognized as the main cause leading to subthreshold swing ( SS ) saturation and degradation of short-channel MOSFETs at cryogenic temperatures. Generally, at a given low temperature, the steeper constant SS of thermionic currents may be overwhelmed by less-steep SDT currents at lower gate bias, degrading the average SS . Our simulations show that the SS of SDT currents is insensitive to temperatures for a MOSFET with a given channel length, accounting for SS saturation as lowering temperature. This work reveals the key points differentiating the possible reasons (interface traps, band tail and SDT) of SS saturation at cryogenic temperatures. We also study the impacts of carrier effective masses, gate-SD underlapping and a tunneling barrier at the source junction on SS saturation. SDT may pose a potential challenge and limit for scaling cryogenic CMOS of a quantum processor.

In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with ID change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of Id. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various VD from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.

Germanium is a promising alternative material for use in advanced technology nodes because it exhibits symmetrical mobility of holes and electrons. Embedded nonvolatile memory (NVM) is essential in electronic devices with integrated circuit (IC) technology, including future Ge-based technology. In this paper, we demonstrate Ge twin-transistor NVM with a fin field-effect transistor (FinFET) structure. This Ge twin-transistor NVM exhibits high programming and erasing speeds and satisfactory reliability. Moreover, the masks and fabrication process of this Ge twin-transistor NVM are identical to those of Ge-channel FinFETs. Thus, Ge twin-transistor NVM is a promising candidate for embedded NVM applications in future high-performance Ge complementary metal-oxide-semiconductor technology (CMOS).

The rapid reduction of feature size in CMOS devices causes their variability to increase, thus reducing the circuit yield [1]-[3]. In particular, the static random access memory (SRAM) cell uses the smallest transistor to achieve high-density integration, the effect of which is a lower yield [4]. The reduction of variability is, therefore, becoming the most important concern for CMOS devices. In this article, we review the effectiveness of introducing multigate devices and microwave annealing (MWA) for performance enhancement.

Monolithic 3D-IC is one of the solutions to relieve Moore’s law with vertically integrating circuits for sub-1nm technology nodes. Therefore, thin-film transistors (TFTs) play an important role in this trend because of their low fabrication temperature to realize back-end circuits. On the other hand, 3D integrating filter, duplexer, switch, and so on is necessary as antennas array requirements increase in 5G or beyond. Consequently, it is foreseeable to adopt TFTs to implement radio frequency (RF) devices. Fig. 1 shows the schematic ideal 3D SoC for sub-1nm technology. Our previous research tried to demonstrate high-frequency back-end devices based on the gate-all-around stacked nanosheet low-temperature polycrystalline silicon channel (GAA NS LTPS). Fig.2 shows the current-voltage transfer characteristics of different width designs of LTPS and α-IGZO devices. The only way to enhance GAA NS LTPS RF devices with the same process is by increasing channels. However, it leads to a larger footprint, and the frequency doesn’t boost with increasing channels in proportion because of the capacitance between the multiple channels. In the meantime, the LTPS gate controllability becomes poor, and threshold voltage shifts significantly when the drive current is improved by widening channel width. Consequently, a-IGZO is adopted as the channel material of RF devices to solve the problem mentioned above. The a-IGZO film is back-end compatible and has transparency and high uniformity. The most important is that the gate controllability decay phenomenon is negligible no matter what the channel width is, which is helpful for different width designs. In contrast, IGZO devices can keep their threshold voltage and have ultra-low leakage current due to a large bandgap. According to the system on panel (SoP) trend, we attempt to integrate RFIC with the peripheral circuit on a substrate. Therefore, a-IGZO is also introduced as a pull-down transistor in a CMOS for power reduction and process simplicity. To further minimize the footprint, the a-IGZO devices are nanoscale and stacked on the p-type LTPS as the defined heterogeneous CFET (HCFET), which is demonstrated in the previous study [1]. In this talk, we will discuss HCFET architecture in detail. We compared junctionless mode (JL) and inversion mode (IM) for bottom p-type LTPS in HCFET. In our results, IM is better than JL as the junction structure for bottom PMOS because the requirement of the bottom channel in a HCFET is thin and width flexible for design. In addition, a trench gate of the bottom device plays an important role in HCFET. The trench tri-gate structure can avoid gate dielectric damage by plasma in the etching process, keep the top IGZO layer continuously and enhance performance compared to the general tri-gate structure. On the other hand, the gate of top n-type IGZO can be bottom gate only or dual gate for different requirements. Finally, HCFET can significantly reduce the distance between IGZO and p-type LTPS channels to save power and lower latency in the circuit. [1] S. -W. Chang et al., "First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2101-2107, April 2022, doi: 10.1109/TED.2021.3138947. Figure 1

We have demonstrated a thermally managed Si nanopillar/SiGe composite structure. Our fabricated defect-free Si nanopillar channel structure showed a 1/100 times lower thermal conductivity than Si bulk thanks to the control of the phonon transports. The results of thermal conductivity measurements clarified that the nanopillar structure could eliminate electron-phonon scattering. As such, this structure represents a promising solution for advanced CMOS technologies.

This study proposes a logic non-volatile memory (NVM) device based on the state-of-the-art gate-all-around (GAA) nanosheet process. By adopting a complementary FET structure, we not only reduce the layout footprint area but also demonstrate the compatibility with sub-3nm nanosheet CMOS technology. We simulated the device in TCAD for program and erase operations, considering both Fowler Nordheim tunneling and hot carrier injection mechanisms. The memory window is optimized by adjusting the device structure, such as tunneling and blocking oxide thicknesses, top- and bottom-channel width, and the floating gate length, resulting in a significant enhancement in the memory window. Finally, NAND/NOR type CFET logic NVM are demonstrated to reveal the possible applications of gate-all-around stacked junctionless nanosheet transistor towards embedded flash.

In this article we proclaim excellent improvement in the defect densities in hafnium zirconium oxide based ferroelectric film obtained by extending the duration of post-metallization annealing up to 180s. The consequences of extending the annealing duration on the structure and surface morphology was gauged by XRD analysis, HR-TEM and AFM, which showed increase in the grain size, well defined crystallinity, lower defect densities and negligible impact on surface roughness. The electrical characterization revealed reduction in RC leakage along with a significant improvement in flicker noise and random telegraphic noise characteristics, which proves reduction of defect densities when the annealing time is increased.

This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from $25\text{nm}$ to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier lowering effects. The improvement is found to be significantly more prominent for short channel devices than long ones, which demonstrates the tremendous advantage of negative capacitance gate stack for scaled MOSFETs. A compact analytical formulation is developed to quantify sub-threshold swing improvement for short channel devices.