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A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm double patterning lower level metals - with yield-friendly single color pitch of 95nm and M1 special constructs with 90nm (=gate pitch) single color pitch for cell abutment - were used for achieving ~2× gate density. Single patterning 80nm pitch metal for routing levels was optimized for both density and performance. Active/passive device and double pattern metal mask count was optimized to reach process should-cost goals. Resulting technology provides cost reduction vs 28 HKMG per close to historical trend, and also cost-competitiveness vs 28 PolySiON. Leveraging of yield learning of this common back-end metallization results in up to 6 month pull-in of 16nm Finfet node yield ramp.

In this work we have demonstrated, for the first time, a 0.605µm2 dual core oxide (DCO) dual Vdd 8T SRAM cell in 45LPG triple gate oxide CMOS process for use as L1 cache for high performance low leakage mobile applications. The DCO 8T SRAM operates under dual voltage supplies with write assist. Compared to traditional single-end 8T cell, DCO 8T SRAM showed the same performance with only half the standby leakage, and lower Vccmin. The PU Vt and dual core oxide boundary were optimized to achieve robust Vccmin, process margin and reliability. The 45LPG thin core transistors and the DCO 8T SRAM are able to achieve 1.5GHz speed with ∼500mW at 0.9V and a low Vccmin of 0.6V.

Si dopant incorporation in GaAs layers is shown to be reduced when dimer arsenic is used. Si doped GaAs layers grown by molecular beam epitaxy under different arsenic cracker conditions are studied by a Polaron doping profiles and secondary ion mass spectrometry. Throughout the doping range of investigation, 5X1016 to 2X1018 cm−3, strong reduction in Si incorporation is observed as the fraction of dimer arsenic is increased. The reduction of Si incorporation is enhanced as the growth temperature is increased. Evidence is given to show that, instead of Si self-compensation, Si dopants are actually desorbed in the presence of dimer arsenic. The formation of volatile SixAsy compound(s) due to the reaction between the impinging dimer arsenic species and the Si dopants at the substrate surface may be responsible for this phenomenon. The activation energy of this reaction is estimated.

A highly scaled, high performance 45 nm CMOS technology utilizing extensive immersion lithography to achieve the industry's highest scaling factor with ELK (k=2.55) BEOL is presented. A record gate density 2.4X higher than that of 65 nm is achieved. Refined strained-CMOS demonstrated 1200/750 μA/μm Idsat at 100 nA/μm Ioff, Vdd=1 V, which has the best Ion-Lg performance reported for bulk CMOS device. The proposed 45 nm technology is not only manufacturing friendly but also has well-controlled leakage and mismatch evidenced by a functional 32 Mb 0.242 μm2 SRAM.

This paper presents the design, fabrication, and characterization of high-performance 0.1 /spl mu/m-channel CMOS devices with dual n/sup +p/sup +/ polysilicon gates on 35 /spl Aring/-thick gate oxide. A 22 ps/stage CMOS-inverter delay is obtained at a power supply voltage of 1.5 V. The highest unity-current-gain frequencies (f/sub T/) measured are 118 GHz for nMOSFET, and 67 GHz for pMOSFET. >

The ability to reduce device features to increasingly smaller dimensions offers the potential for remarkable circuit performance and low power consumption. CMOS (Complementary Metal-Oxide-Semiconductor) devices with 100 nm channel lengths offer a 2X performance gain over 0.25 μm technology at a reduced power supply as well as the potential for a 20X reduction in active power at comparable performance levels. Continued scaling of devices beyond 100 nm dimensions faces various fundamental limitations. Overcoming these limitations will require technological innovation in both device design and fabrication.

Activation techniques have been used to measure the cross sections for the 39K(n, 2n)38gK reaction at neutron energies between 14.4 and 18.2 MeV, the cross sections for the 41K(n, α)38Cl reaction from 14.4 to 16.3 MeV and the cross sections for the 41K(n, p)41Ar reaction from 14.4 to 17.3 MeV. Gamma-rays from the decay of the residual nuclei were detected with an HPGe detector whose energy resolution at 1.33 MeV is approximately 1 keV fwhm. The mixed powder method was employed to determine the neutron flux at each neutron energy, and the associated particle method was used to check the mixed powder flux measurements at 14.4 and 15.4 MeV. Good agreement was obtained for the average cross sections computed using both methods. Measured cross sections for the 39K(n, 2n)38gK reaction are 2.2 ± 0.2, 5.8 ± 0.4, 6.6 ± 0.5, 14.4 ± 0.9 and 22.1 ± 1.5 mb at 14.4 ± 0.2, 15.4 ± 16.3 ± 0.1, 17.3 ± 0.1 and 18.2 ± 0.1 MeV, respectively. Cross sections for the 41K(n, p)41Ar reaction are 52.9 ± 2.6, 44.9 ± 2.1, 41 and 34.2 ± 3.0 mb, respectively for the first four neutron energies listed above, and, for the first three energies, the cross sections for the 41K(n, α)38Cl reaction are 34.4 ± 2.4, 28.5 ± 2.2 and 24.5 ± 2.6 mb.