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Herein, we successfully improved the maximum oscillation frequency and maximum stable gain (MSG) across a wide bias range of surface-oxide-controlled (SOC) InGaAs/InAlAs inverted-type metal-oxide-semiconductor high-electron-mobility transistors (inverted MOS-HEMTs) by reducing the gate leakage current and drain conductance (g d). H2O vapor treatment selectively decreased the narrow band gap indium oxide at the surface of the In-based epitaxial layer via the SOC process before the gate oxide deposition. Furthermore, the calculation of band profiles indicated that the gd reduction was possibly attributed to the suppression of impact ionization in the InGaAs channel by inverted MOS-HEMTs. Consequently, SOC-inverted MOS-HEMTs demonstrated a high MSG of >12 dB at 100 GHz across a wide bias range.

The minimum noise figure (NFmin) at 94 GHz was improved effectively by employing a cavity structure in the interconnection process, even though a wide gate head was used in InP-based high-electron-mobility transistors (HEMTs). The wide gate head is effective in improving NFmin since gate resistance is reduced, while increased parasitic capacitance at a passivated gate affects the noise figure. Then, the parasitic capacitance was eliminated successfully by employing a cavity structure around the gate region. We measured an NFmin of 0.9 dB when the cavity structure was employed in the wide-gate-head HEMTs.

This paper describes a full-rate-clock 4:1 multiplexer (MUX) in a 0.13-/spl mu/m InP-based HEMT technology for 40-Gb/s and above optical fiber link systems. To reduce output jitter, the serialized data are retimed at the final stage by a retimer, a D-type flip-flop, which has a symmetric layout with an optimized spacing to the ground that minimizes coupling capacitances. A phase adjuster, composed of an exclusive OR and a delay switch, uses external control signals to change each phase of the serialized data and clock entering the retimer and gives a correct timing for the clock to drive the retimer. A clock distributor with a simple wired splitter divides the clock into two clocks with high gain and low current. The MUX integrates 1355 HEMTs formed using electron beam lithography. A chip mounted in a test module operated at up to 47 Gb/s with a power consumption of 7.9 W for a single supply voltage of -5.2 V.

An asynchronous-transfer-mode (ATM) switch LSI was designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6- mu m high-electron-mobility-transistor (HEMT) technology. To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled logic was used instead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8-mm*4.7-mm chip contains 7100 DCFL gates. The maximum operating frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An experimental 4-to-4 ATM switching module using 16 switch LSIs achieved a throughput of 38.4 Gb/s. >

An asynchronous transfer mode (ATM) switch LSI has been designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6- mu m high-electron-mobility transistor (HEMT) technology. To enhance the high-speed performance of direct coupled FET logic (DCFL), event control logic was used for the first-in first-out (FIFO) buffer circuit, instead of conventional static memory. The 4.8-mm*4.7-mm chip contains 7100 DCFL gates. The maximum operation frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. >

We developed a novel design technique for a D-type flip-flop (D- FF) circuit that is based on a small-signal-equivalent circuit approach. This technique provides the best condition to operate the D-FF at a high frequency. Using this technique, we fabricated a master-slave D-FF using a 0.15-/spl mu/m InP HEMT technology. We achieved 40-Gbit/s operation with clear-eye-waveform patterns and reduced jitter.