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We examined the effect of backside insulation on the dynamic on-resistance of lateral p-GaN HEMTs. To gain a comprehensive understanding of the dynamic onresistance difference between substrate grounded and substrate floating p-GaN HEMTs, we conducted in-circuit double pulse testing and long-term direct current (DC) bias stress. We have realized that while backside insulation can enhance the breakdown voltage of lateral p-GaN HEMTs, it also comes with a tradeoff in device reliability. Results through Sentaurus TCAD simulation suggest that the use of backside insulation in devices gradually disperses potential to the buffer barrier. As a result, the potential barrier at the buffer edge of the 2DEG channel decreases significantly, leading to considerable electron trappings at buffer traps. This breakdown voltage and reliability tradeoff also applies to HEMT technologies using insulating substrates.

Our study focused on the Ge thickness and TDD impacts on Ge's photoluminescence (PL). The PL peak intensity of a bulk Ge sample (TDD = 6000 cm-2, n-doping = 1e16 cm-3) experiences a remarkable 32-fold increase as the thickness is reduced from 535 to 2 microns. This surpasses the PL peak intensity of a best-performing epitaxial-Ge on Si (epi-Ge) (0.75 micron thick, biaxial tensile strain= 0.2 percent, n-doping = 7e18 cm-3) by a factor of 2.5. Furthermore, the PL peak intensity of a 405-micron thick zero-TDD bulk Ge sample (n-doping = 5e17 cm-3) is 9.7 times that of the 0.75-micron thick epi-Ge, rising to 12.1 times when thinned to 1 micron. The bulk Ge-based TDD reduction approach can work in conjunction with n-type doping and strain engineering to enhance Ge laser performance, and relax the requirement on the latter two approaches.

Low-defect-density Ge thin films are critical in Ge based optical devices (optical detectors, LEDs and Lasers) integrated with Si electronic devices for low-cost, highly integrated photonic circuits. In this work, Ge thin films prepared by wet etching with four different solutions were studied in terms of the surface morphology, defect density and achievable thickness. Both nanostrip-based solution (1:1:10) and HCl-based solution (1:1:5) were able to wet-etch 535 micron thick bulk-Ge substrates to Ge films thinner than 10 micron within 53 hours. The corresponding RMS surface roughness was 32 nm for the nanostrip-based solution and 10 nm for the HCl-based solution. The good quality of bulk-Ge was preserved before and after the etching process according to the HRXRD results. The low threading dislocation density of 6000-7000 cm-2 was maintained in the process of wet etching without introducing extra defects. This approach provides an inexpensive and convenient way to prepare sub-10-micron thick Ge thin films, enabling future studies of low-defect-density Ge-based devices such as photodetectors, LEDs, and lasers.

This work investigated the small signal performance of Fabry-Perot Ge-on-Si lasers by modeling and simulations. The 3dB bandwidth dependence on the structure parameters such as poly-Si cladding thickness, Ge cavity width and thickness, and minority carrier lifetime were studied. A 3dB bandwidth of 33.94 GHz at a biasing current of 270.5 mA is predicted after Ge laser structure optimization with a defect limited carrier lifetime of 1 ns.

We present a novel p-GaN gate HEMT structure with reduced hole concentration near the Schottky interface by doping engineering in MOCVD, which aims at lowering the electric field across the gate. By employing an additional unintentionally doped GaN layer, the gate leakage current is suppressed and the gate breakdown voltage is boosted from 10.6 to 14.6 V with negligible influence on the threshold voltage and on-resistance. Time-dependent gate breakdown measurements reveal that the maximum gate drive voltage increases from 6.2 to 10.6 V for a 10-year lifetime with a 1% gate failure rate. This method effectively expands the operating voltage margin of the p-GaN gate HEMTs without any other additional process steps.

We report a dramatic current reduction, or a resistance increase, by a few orders of magnitude of two common-anode Au/Ti/pGaN Schottky junctions annealed within a certain annealing condition window (600 - 700 oC, 1 - 4 min). Results from similar common-anode Schottky junctions made of Au/p-GaN, Al/Ti/p-GaN and Au/Ti/graphene/p-GaN junctions demonstrated that all the three layers (Au, Ti and p-GaN) are essential for the increased resistance. Raman characterization of the p-GaN showed a decrease of the Mg-N bonding, i.e., the deactivation of Mg, which is consistent with the Hall measurement results. Moreover, this high-resistance junction structure was employed in p-GaN gate AlGaN/GaN HEMTs. It was shown to be an effective gate technology that was capable to boost the gate breakdown voltage from 9.9 V to 13.8 V with a negligible effect on the threshold voltage or the sub-threshold slope.

We studied the stability and superconductivity of FeSe nanosheets during an in-air device fabrication process. Methods were developed to improve the exfoliation yield and to maintain the superconductivity of FeSe. Raman spectroscopy, atomic force microscopy, optical microscopy and time-of-flight-secondary-ion-mass-spectroscopy measurements show that FeSe nanosheets decayed in air. Precipitation of Se particles and iron oxidation likely occurred during the decay process. Transport measurements revealed that the superconductivity of FeSe disappeared during a conventional electron beam lithography process. Shadow mask evaporation and transfer onto pre-defined electrodes methods were shown to be effective in maintaining the superconductivity after the in-air device fabrication process. These methods developed provide a way of making high quality FeSe nano-devices.

Side and top silicon nitride stressors were proposed and shown to be effective ways to reduce the threshold current Ith and improve the wall-plug efficiency {\eta}wp of Ge-on-Si lasers. Side stressors only turned out to be a more efficient way to increase {\eta}wp than using top and side stressors together. With the side stressors only and geometry optimizations, a {\eta}wp of 30.5% and an Ith of 50 mA (Jth of 37 kA/cm2) can be achieved with the defect limited carrier lifetime of 1 nsec. With the defect limited carrier lifetime of 10 nsec, an Ith of 7.8 mA (Jth of 5.8 kA/cm2) and a wall-plug efficiency of 38.7% can be achieved. These are tremendous improvements from the case without any stressors. These results give strong support to the Ge-on-Si laser technology and provide an effective way to improve the Ge laser performance.

We investigated 10 to 200 nm thick black phosphorus flakes on SiO2/Si and polyimide substrates by Angle-resolved Polarized Raman spectra (ARPRS) using 442 nm excitation wavelength. The results revealed that ARPRS with 442 nm excitation can provide unambiguous, convenient, non-destructive and fast determination of BP's crystallographic orientation. The substrate and thickness dependencies of Raman spectra and Raman tensor elements were studied. These dependencies were shown to be influenced by Raman excitation laser heating effect. By comparing with in-situ Raman measurements at elevated temperatures, we were able to quantify the laser-heating effect, which is significant and hard to avoid for Raman measurements of BP on polyimide substrates due to the poor thermal conductivity of the substrate. Thermal processing by substrate heating was shown to have a significant impact on BP on SiO2/Si substrate, but not for BP on polyimide due to smaller thermal expansion mismatch. Our results give important insights on Raman Spectroscopy characterizations of BP on different substrates., Comment: 45 pages, 300 figures

High quality AlxGa1-xAs distributed Bragg reflectors (DBRs) were successfully monolithically grown on on-axis Si (100) substrates via a Ge layer formed by aspect ratio trapping (ART) technique. The GaAs/ART-Ge/Si-based DBRs have reflectivity spectra comparable to those grown on conventional bulk off-cut GaAs substrates and have smooth morphology, and good periodicity and uniformity. Anitphase domain formation is significantly reduced in GaAs on ART-Ge/Si substrates, and etch pit density of the GaAs base layer on the ART-Ge substrates ranges from 10^5 to 6 x 10^6 cm^(-2). These results paved the way for future VCSEL growth and fabrication on these ART-Ge substrates and also confirm that virtual Ge substrates via ART technique are effective Si platforms for optoelectronic integrated circuits.

Micro-Raman spectroscopy was employed to study the near-surface stress distributions and origins in Si around through silicon vias (TSVs) at both room temperature and elevated temperatures for Cu-filled and CNT-filled TSV samples. From the observations, we proved that the stresses near TSVs are mainly from two sources: 1) pre-existing stress before via filling, and 2) coefficients of thermal expansion (CTE) mismatch-induced stress. CTE-mismatch-induced stress is shown to dominate the compressive regime of the near-surface stress distribution around Cu-filled TSV structures, while pre-existing stress dominates the full range of the stress distribution in the CNT-filled TSV structures. Once the pre-existing stress is minimized, the total stress around CNT-filled TSVs can be minimized accordingly. Therefore, compared to Cu-filled TSVs, CNT-filled TSVs hold the potential to circumvent the hassle of stress-aware circuit layout and to solve the stress-related reliability issues.

Physical models of Ge energy band structure and material loss were implemented in LASTIP(TM), a 2D simulation tool for edge emitting laser diodes. The model calculation is able to match experimental data available. Important design parameters of a Fabry-Perot Ge laser, such as the cavity length, thickness, width, polycrystalline Si cladding layer thickness were studied and optimized. The laser structure optimizations alone were shown to reduce Ith by 22-fold and increase the differential efficiency by 11 times. The simulations also showed that improving the defect limited carrier lifetime is critical for achieving an efficient and low-threshold Ge laser. With the optimized structure design (300 micron for the cavity length, 0.4 micron for the cavity width, 0.3 micron for the cavity thickness, and 0.6 micron for the polycrystalline Si cladding layer thickness) and a defect limited carrier lifetime of 100 ns, a wall-plug efficiency of 14.6% at 1mW output is predicted, where Jth of 2.8 kA/cm2, Ith of 3.3 mA, I_1mA of 9 mA, and differential efficiency of 23.6% can also be achieved. These are tremendous improvements from the available experimental values at 280 kA/cm2, 756 mA, 837 mA and 1.9%, respectively., Comment: 12 pages, 9 figures