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We analyze the benefits of replacing selected MOSFET transistors by nanoelectromechanical relays within conventional CMOS six transistor SRAM cells. Specifically, we evaluate a potential implementation that uses a cantilever designed with a 65 nm standard CMOS technology. The impact on various reliability metrics like static noise margin and write noise margin are evaluated from circuit simulations using a nanomechanical relay Verilog-A compact model. Comparisons are performed between a 65 nm CMOS 6T conventional SRAM cell and various hybrid memory cells constructed by replacing selected MOSFET transistors with cantilever relays. The impact on other important memory cell parameters such as area, timing performance and power consumption is also discussed.

We report and analyze the dependence of complex gates delay with the sensitization vector and its variation-that gets up to 40% in 65-nm CMOS technologies-and include its effect in the path delay estimation-that can be in the order of 16%. The gate delay is computed from a simple polynomial analytical description that requires a one-time library parameter extraction process, making it highly scalable. An STA tool based on a single-pass true path computation is used to determine the critical path list. Since it does not rely on a two-step process, it can be programmed to find efficiently the N true paths from a circuit. Results from various benchmark circuits synthesized for three commercial technologies (130, 90, and 65 nm) provide better results in number of paths reported and delay estimation for these paths compared to a commercial tool. The impact of delay variation with the sensitization vector for paths with complex gates reveals as a significant mechanism that must be considered as it is comparable to the impact of parameter variations or interconnect-induced delay.

We present a single event transient (SET) propagation model that can be used to quantify the propagation likelihood of a given noise waveform trough CMOS logic gates. This analysis is key to predict if an SET induced within a combinational block is capable of causing an SEU. The model predicts the output noise characteristics given the input noise waveform for each gate, and can be applied to any CMOS technology through a one-time library parameter extraction process. Pulse propagation is described through continuous analytical functions that convert an SET pulse height and width at the gate input to an SET pulse height and width at its output. The noise transfer curves have relatively simple analytical continuous expressions suitable for an easy adoption within CAD tools, thus allowing the investigation of pulse propagation through an entire logic block. Comparison between simulations and model show a very good agreement for a commercial 65 nm technology.

We analyze the design constraints of six transistor SRAM cells that arise when using nanoelectromechanical relays. Comparisons are performed between a CMOS 6T conventional SRAM cell and various hybrid memory cells built by replacing a selection of MOSFET transistors with NEM relays. Impact on important memory cell parameters such as various reliability metrics like static noise margin and write noise margin and power consumption are evaluated from circuit simulations using a Verilog-A compact model of the nanomechanical relay. We found that the use of relays involve a new challenge in the design of SRAM hybrid devices as the readability and writeability of the resulting cells manifests a strong dependence with the value of the contact resistance of the NEM relay, a parameter that can experience important variations with the continued operation of the device.

We present a glitch propagation model that can be used to categorize the propagation likelihood of a given noise waveform trough a logic gate. This analysis is key to predict if a SET induced within a combinational block is capable of causing a SEU. The model predicts the glitch output characteristics given the input noise waveform for each gate in a 65- nm technology library. These noise transfer curves are fitted to known functions to have a simple analytical equation and compute the propagation. Comparison between simulations and model shows a good agreement.

We present a STA tool based on a single-pass true path computation that efficiently determines the critical path list Given that it does not rely on a two-step process it can be programmed to find efficiently the N true paths from a circuit We also report and analyze the dependence of complex gates delay with the sensitization vector and its variation (that gets up to 15% in 6Snm technologies), and consider such effect in the path delay estimation Delay is computed from a simple polynomial analytical description that requires a one-time library parameter extraction process, making it highly scalable. Results on combinational ISCAS synthesized for three technologies (130nm, 90nm and 6Snm) provide better results in computation time, number of paths reported and delay estimation for these paths compared to a commercial tool.