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This article presents an algorithm for integrated timing-driven latch placement and cloning. Given a circuit placement, the proposed algorithm relocates some latches while circuit timing is improved. Some latches are replicated to further improve the timing; the number of replicated latches along with their locations are automatically determined. After latch cloning, each of the replicated latches is set to drive a subset of the fanouts that have been driven by the original single latch. The proposed algorithm is then extended such that relocation and cloning are applied to some latches together with their neighbor logic gates. Experimental results demonstrate that the worst negative slack and the total negative slack are improved by 24% and 59%, respectively, on average of test circuits. The negative impacts on circuit area and power consumption are both marginal, at 0.7% and 1.9% respectively.

Fast data communication is the need of today’s generation. This is because of the advancements and growth of technologies. This research work is about the implementation and analysis of data communication of Universal Asynchronous Receiver Transmitter (UART) on Kintex-7 Field Programmable Gate Array (FPGA) at different clock periods. The implementation is done on the VIVADO tool and analysis of data communication for different clock time is done by timing summary option available on the VIVADO tool. It is observed that data communication takes place in UART when the clock period is 3ns or more than 3ns because for the data transfer Worst Negative Slack (WNS) and Worst Hold Slack (WHS) both must be positive and Total Hold Slack (THS) and Total Negative Slack (TNS) should be 0.000. If the clock period is less than 3ns no data transfer will take place.

Closing timing using clock tree optimization (CTO) is a tremendously challenging problem that may require designer intervention. CTO is performed by specifying and realizing delay adjustments in an initially constructed clock tree. Delay adjustments are typically realized by inserting delay buffers or detour wires. In this paper, we propose a latency constraint guided buffer sizing and layer assignment framework for clock trees with useful skew, called the (BLU) framework. The BLU framework realizes delay adjustments during CTO by performing buffer sizing and layer assignment. Given an initial clock tree, the BLU framework first predicts the final timing quality and specifies a set of delay adjustments, which are translated into latency constraints. Next, buffer sizing and layer assignment is performed with respect to the latency constraints using an extension of van Ginneken's algorithm. Moreover, the framework includes a feature of reducing the power consumption by relaxing the latency constraints and a method of improving the timing performance by tightening the latency constraints. The experimental results demonstrate that the proposed framework is capable of reducing the capacitive cost with 13% on the average. The total negative slack (TNS) and worst negative slack (WNS) are reduced with up to 58% and 20%, respectively.

In this paper, we study a fundamental and crucial problem of building timing-driven over-the-block rectilinear Steiner tree (TOB-RST) with pre-buffering and slew constraints. We pre-characterize the tree topology and buffer distribution to provide accurate timing information for our final RST construction. In most previous work, the routing resources over the IP blocks were simply treated as routing blockages. Our TOB-RST could reclaim the ``wasted'' over-the-block routing resources while meeting user-specified timing (slack and slew) constraints. Before fixing topology, a topology-tuning is performed based on location of buffers to improve timing without increasing buffering cost. Experiments demonstrate that TOB-RST can significantly improve the worst negative slack (WNS) with even less buffering and wirelength compared with other slack-driven obstacle-avoiding rectilinear Steiner tree (SD-OARST) algorithms.

A fundamental challenge addressed by physical synthesis is reducing circuit delay by altering timing-critical paths. Several techniques can be applied to achieve this optimization: buffer insertion, gate sizing, cell movement, etc. In this work, we propose a powerful new technique that moves and resizes multiple cells simultaneously to straighten critical paths, thereby reducing delay and improving worst negative slack.