1. A Highly Reliable and Cost Effective 16nm Planar NAND Cell Technology
- Author
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Lin Li, Niccolo Righetti, Christopher J. Larsen, David Daycock, S. Beltrami, Akira Goda, M. Bertuccio, Matthew J. King, Jeff Karpan, Giuseppina Puzzilli, Ceredig Roberts, Ricardo Basco, Elisa Camozzi, and William Kueber
- Subjects
Non-volatile memory ,Planar ,Interference (communication) ,Stack (abstract data type) ,AND-OR-Invert ,Computer science ,Logic gate ,Electronic engineering ,NAND gate ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Gate equivalent ,Hardware_LOGICDESIGN - Abstract
A 2D 16nm planar NAND cell technology is described with good cell to cell interference and reliability that can be used in a wide variety of applications. This second generation planar cell uses a high-K dielectric stack and a thin poly floating gate to maintain the needed gate coupling ratio and reduce adjacent cell interference. The technology includes select gates with the same planar structure as the cell. This select gate architecture simplifies the manufacturing of this NAND technology.
- Published
- 2015
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