Back to Search Start Over

A Highly Reliable and Cost Effective 16nm Planar NAND Cell Technology

Authors :
Lin Li
Niccolo Righetti
Christopher J. Larsen
David Daycock
S. Beltrami
Akira Goda
M. Bertuccio
Matthew J. King
Jeff Karpan
Giuseppina Puzzilli
Ceredig Roberts
Ricardo Basco
Elisa Camozzi
William Kueber
Source :
2015 IEEE International Memory Workshop (IMW).
Publication Year :
2015
Publisher :
IEEE, 2015.

Abstract

A 2D 16nm planar NAND cell technology is described with good cell to cell interference and reliability that can be used in a wide variety of applications. This second generation planar cell uses a high-K dielectric stack and a thin poly floating gate to maintain the needed gate coupling ratio and reduce adjacent cell interference. The technology includes select gates with the same planar structure as the cell. This select gate architecture simplifies the manufacturing of this NAND technology.

Details

Database :
OpenAIRE
Journal :
2015 IEEE International Memory Workshop (IMW)
Accession number :
edsair.doi...........c49a1a003c2658e42a42b17b10dc09b6
Full Text :
https://doi.org/10.1109/imw.2015.7150269