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Multi-phase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this paper we propose a MPCG design with two major innovations: (1) We use a process calibration scheme that makes the per-phase delay (defined as the timing difference between two consecutive clock signals) highly accurate. (2) We further exploit a so-called cyclic property to make the achievable per-phase delay much smaller than a buffer delay. The entire design can be made in all standard cells, thus lending itself to automation. Experimental results indicate this design is highly general and can be applied to a 16-phase clock signal (with the per-phase delay of only 100ps) for a practical radar SoC design. [ABSTRACT FROM PUBLISHER]