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Abstract The analysis of magnetic near‐field radiation emissions (MNRE) has recently raised more attention in device‐level electromagnetic compatibility testing. Pattern clustering of MNRE for integrated circuits manually is very time‐consuming because of the multi‐dimensional characteristics of MNRE, such as frequency, spatial position, emission intensity, etc. This paper proposes a novel pattern clustering method of MNRE, including strong emission frequency extraction, feature extraction, and density‐based clustering. Ring oscillator and five working states are designed on a Field Programmable Gate Array with 256 Ball Grid Array package, which are used to create a complex multi‐source emission case for verifying the effectiveness of the clustering method. The verification results show that the proposed method can correctly cluster the multi‐source emission patterns. Further, the method is also applied to a Microcontroller Unit with unknown operating states; the results show that the proposed method also can effectively distinguish the unknown emission patterns and locate the unknown interference source. The accuracy of the interference source location is proven by 3D X‐ray microscope inspection.

In this paper, a high-performance and low-HCI (Hot carrier injection) degradation LDMOS (Lateral double diffused metal oxide semiconductor) device is introduced. It consists of an additional mini LOCOS (Local oxidation of silicon) field plate combined with a mini STI (Shallow trench isolation) field plate without an additional complex fabrication process. A series of devices have been fabricated, and the field plate corner profile is optimized. The proposed hybrid FP(Field plate) can effectively reduce the electric field peak, and the BV (Breakdown voltage) achieves as high as 78.9V while the ${R}_{{on}{,}{sp}}$ (Specific on-resistance) is as low as $69.1~{{\mathrm { m}}\Omega \cdot }{mm}^{2}$ , which is 65.8% improved compared with conventional transistors. Meanwhile, the hybrid FP device owns much better HCI (Hot carrier injection) degradation performance on ${R}_{on,sp}$ , threshold voltage ${V}_{T}$ , and gate-drain capacitance ${C}_{GD}$ . The degradation of ${R}_{{on}{,}{sp}}$ is only 8.6% under ${I}_{d}$ mode stress while it is as high as 15.8% for the conventional devices. At on-state, ${C}_{GD}$ degradation is only 9.1% while it is nearly 59.9% in the traditional device. At high voltage application regions, the device exhibits nearly 0% ${C}_{GD}$ degradation while it is as high as 43.8% in the traditional device. The results indicate the device’s robustness in both DC (Direct current) applications and RF (Radio frequency) applications.

The design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low $R_{\mathrm{ on,sp}}$ (Specific on-resistance) LDMOS device is simulated, designed, and fabricated. The effects on FOM (Figures-of-merits) characters from physical dimensions, including field plate length ${L}$ , field plate thickness ${H}$ , and slot contact width ${W}$ , have been analyzed and discussed. The best device structure is proposed through simulation, and a related fabrication process is introduced correspondingly. Finally, the electrical measurement results show that $R_{\mathrm{ on,sp}}$ can achieve as low as 6.9m $\Omega \cdot $ mm2 when the source-drain ${BV}$ (Breakdown voltage) arrives at 34.1V, which is improved by 47.1% compared with conventional devices. Furthermore, the TLP (Transmission line pulse) test results indicate that the device owns an ideal SOA (Safe operation area) from both typical devices (W $=\,\,10~\mu \text{m}$ ) and very large devices (W = 2mm).

Abstract The de‐embedding calibration method has been proposed to achieve high‐precision calibration for a single port electric field or magnetic field probe, which can effectively eliminate the calibration ripple. However, the method's effectiveness for a four‐port calibration system has not been verified yet. In this paper, a four‐port de‐embedding calibration method with a differential magnetic field probe is proposed, and its effectiveness is proved. Two symmetric grounded coplanar waveguide transmission lines are applied in the proposed method to solve the ABCD‐matrix of the embedded part of the calibrator. The de‐embedded S‐parameter model of the four‐port calibration system for differential magnetic field probe can be obtained. The calibration results indicate that the proposed method can also reduce the calibration ripple and compensate for the attenuation caused by the calibrator. Compared with the traditional calibration method using a microstrip line calibrator, the ripples of the proposed method can be reduced by 34%. The analysis results of the frequency interval of the ripple (FIR) in different methods show that the de‐embedding method can reduce the FIRs (except around 1.2 GHz) caused by the reflection of the calibrator and retain the FIR (about 1.2 GHz) caused by the reflection of the probe itself.

Abstract This paper develops an active magnetic near field probe (H‐field probe) by using a four‐layer printed circuit board (PCB) technique. Two‐turn detection structure and a low noise amplifier are used to improve probe's frequency response. The two‐turn detection structure can maximize the use of PCB stack resources, and a 14.5 dB gain amplifier can increase signal output capability. The probe can then be used for electromagnetic compatibility (EMC) test from 150 kHz to 3 GHz. Compared with traditional active shielded‐loop H‐field probe (TAHP) with loop area of 500 μm2, the frequency response of the proposed probe can improve 20 dB at 0.5 GHz. Different from the method of comparing the sensitivity of the probe only through the frequency response, this paper measures and analyzes the real sensitivity of the probing device composed of the proposed probe. Under the condition of the same receiver parameter setting, the sensitivity at 0.5 GHz is increased by 11.7 dB compared with commercial passive probing device and 20.2 dB at 0.5 GHz compared with the probing device with TAHP device. It reaches −32.4 dB μA. In addition, the proposed probe has acceptable spatial resolution of 1.28 mm at 1 GHz, which is more suitable for printed circuit board level EMI analysis.

In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ2 is improved from 11.9° to 12.6°, and the thickness ratio of Hup/Hbottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance Ron,sp could achieve as low as 11.3 mΩ mm2, while breakdown voltage BVds,max arrives at 37.4 V, which is nearly 19.3% improved.

Abstract A magnetic near‐field probe (H‐field probe) with dual output has been developed using a four‐layer printed circuit board (PCB) technique. To achieve the improvement of detection sensitivity, the symmetrical double‐loop is adopted to double the detection signal while suppressing the electric field coupling, which is also illustrated in a circuit model. The calibration factor (defined as the ratio of the external magnetic field to the induced response voltage of the probe) of the proposed H‐field probe reaches 37.74 [dB (A/m)/V] at 0.5 GHz with the loop area of 0.8 mm2, resulting in a better sensitivity than the single‐loop probe. For the suppression of unwanted electric field a floating shield is added to the bottom of the probe, leading to an excellent common electric field suppression ratio of 29 dB in the frequency range up to 10 GHz. The probe is also characterised by parameters such as high differential electric field suppression, spatial resolution and probe influence on the device under test.