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Figure Presented. Figure 1 that depicts the 3D structures and y/x-cut profiles of the devices in the article [AIP Adv. 13, 065006, (2023)1] has some errors that need to be corrected, where (b) (3D structureof NW GAAFET) and (c) (3D structure of NT GAAFET); (h)(x-cut profile of NW GAAFet along the channel direction); and (i)(x-cut profile of NT GAAFet along the channel direction) should change their locations with each other. The corrected Fig. 1 appears here. © 2023 Author(s).

With transistors scaling down to 3 nm node and beyond, short channel effect (SCE) as well as power consumption dissipation present immense challenges for further scaling down of the transistor. Hence the Gate all around field effect transistor (GAA-FET) is proposed to replace the Fin field effect transistor (FinFET) in 3 nm technology node and beyond due to its better gate control over the channel with surrounding gate structure, thus providing improved SCE constraint ability. Traditional transistors suffer from the problems of 'Boltzmann Tyranny' and cannot overcome the subthreshold swing (SS) limit of 60 mV/dec at room temperature. To maintain high I on and avoid I off from increasing too much, supply voltage ( VDD ) of the conventional transistor cannot scale down proportionally with the dimension of the transistor. The concept of negative capacitance (NC) has been demonstrated to be able to obtain sub-60 mV/dec SS with the ability of amplifying the potential of the channel region without VDD increment. The novel device structure of negative capacitance gate all around field effect transistor(NC GAA-FET) can combine both the advantages of GAA-FET and NC-FET, and is the most promising ultra-low power consumption device and promises to sustain the Moore's law further beyond what is predicted now. Whereas, according to our knowledge, there have been few review papers about NC GAA-FET till now. Herein, we summarize the recent developments of the NC GAA-FET both in simulation and experimental aspects, which we believe will bring about profound changes to the further development of NC GAA-FET devices. © 2013 IEEE.

We demonstrate the construction of the optical system in the atomic clock-beyond atomic fountain based on Rb-87 atom. The optical system includes a high-stability laser system and an optical lattice. The high-stability laser system with the new scheme of frequency locking and shift is introduced in detail, which is an important laser source for laser cooling. The optimized frequency and intensity stability are achieved to 4 x 10(-14) tau - 1 / 2 ( tau is the averaging time) and 4 x 10(-5) tau - 1 / 2 , respectively, which are highly stable. On the basis of the conventional atomic fountain clock, the optical lattice is specially investigated along the direction of gravity and its characteristics are studied systematically. For the optimized and novel exploration, we predict the achievable stability of 3.6 x 10 - 14 tau - 1 / 2 and it has the potential to be improved to 3.6 x 10 - 15 tau - 1 / 2 . The realizability of the construction due to the stabilized laser and optical lattice makes the beyond fountain promising candidate for the next-generation high performance microwave atomic clock.

Gallium Nitride (GaN) high electron mobility transistors (HEMTs) are invented as promising replace to existing Si and GaAs based devices in the RF/Micro-Wave power amplifiers and high-power switching fields. Along with the fast development of device technology and circuit design methodology, the reliability issue of GaN HEMTs is becoming great challenge for circuit designers and simulator. In this report, the stress reliability of E-mode HEMT at the conductance state is investigated. The characteristic forward gate voltage is verified, once above which the switch voltage shows a little while always negative direction drift. This character seems to be nonrecoverable even rest time over one days while above 400°C high ratio annealing. On the other hand, the enhanced HEMTs show more good reliability once the work voltage less the characteristic gate voltage. The enhanced stability of turn on voltage provides evidence to support the fact the characteristic voltage drift is not external high E-field independent physical phenomenon. These results provide better understanding for GaN HEMT circuit design and device process technology development. © 2020 IEEE.

A surface potential based compact model for GaN HEMT current-voltage (IV) and capacitance-voltage (CV) characteristics simulation is developed in this report. In this new model, the channel charge density is first obtained from self-consistent solution of both Poisson's equation and Schrödinger's equations in the quantum well, and then I-V and C-V model are developed based on the surface potential. And then some real device second effects such as channel length modulation, velocity saturation are incorporated into the core model. Fianlly, the developed model is verified with TCAD simulations, and experimental data of the real devices. © 2020 IEEE.

The compact Modeling of Capacitance Components for GaN HEMTs is presented in this paper. From the charge control equations, the surface potential is modeled analytically. From the surface potential calculation beginning, various terminal intrinsic charges and capacitance expressions are derived self-consistently with developed I-V model. On the other hand, the parasitic capacitance components are expressed by the means of the conforming method and transport line equation. As a result, the full capacitance model for the GaN HEMT devices are established. With the experimental data and simulation, the developed model is evaluated and verified with good agreements with measured and simulation data. © 2020 IEEE.

Vision based hand tracking is an important area of human machine interaction (HCI) and virtual reality techniques. However, it is still a great challenge. Due to the complicated environment and various hand appearances, it is difficult to realize stable and long-term tracking. In this paper, we proposed an effective approach to detect and track hand with a normal webcam. An integrating multi-cue detector with skin color and hand classifier is used to initialize the tracking region and find appearance information during tracking. Also a median flow tracker is integrated which utilizing the motion information to enhance the accuracy in short-term. We realize an automatic system of stable and long-term hand tracking, which can detect and track pre-trained frontal view hand gesture. Experiments show the good performance of our approach.

A numerical model based on the finite element method for phase change memory including ovonic threshold switch and memory threshold switch is developed. The temperature distribution, phase fraction profiles in set operation and the programming resistance variation with currents are simulated respectively. By analyzing the programming properties of cells at different reset state, the impacts of the reset current to the programming characteristics are evaluated.

Parasitic capacitances of phase-change memory (PCM) bitlines which induce RC delay lead to reset failure. To analyze the critical parasitic capacitance of different feature sizes, the transient resistances of PCM cells with different geometries during programming is to be evaluated. In this work, an accurate numerical model including latent heat comparison (LHC) which is able to calculate transient resistance is developed, and a AlST-based PCM cell is simulated. Combining the transient resistance and the periphery parasitic circuit, the impact of the fall time during the end of reset pulse induced by parasitic capacitances is simulated. Results show that reset failure may happen during device scaling down. The method can be used to predict critical parasitic capacitance and critical size of PCM cells with different materials or structures.

The impact of junction formed by the electrode and bulk in phase change memory to conduction at the amorphous high resistance state is studied in this paper. Analytical model deduced from basic physical equation elucidates that the current changes from junction barrier limited to bulk barrier limited when the applied voltage increases. The currents deduced from the model are in highly consistent with the measurement data at different temperatures. It is also found that the junction barrier becomes non-negligible when the radius of bottom electrode is scaled down to 20 nm.

As one of the candidates of the next generation non-volatile memory(NVM), phase change memory(PCM) has been paid more attention. However, there are still many open issues such as numerical simulation to study. Phase transition is a temperature based process, which can be simulated by temperature profile generated by the device simulator coupled with the phase transition model. In this work, a phase transition model is implemented, which can provide the amorphization process simulation and the nucleation process simulation, and the set and reset process are simulated. Meanwhile the readout I-V characteristics are simulated and discussed.

As one of the candidates of the next generation non-volatile memory(NVM), phase change memory(PCM) has been paid more attention. But there are many open issue in simulation and phase-change mechanism. In this work, an electrothermal simulation is implemented, which can provide an evaluation method for PCM geometry and scaling design. At the time, a threshold-switching mechanism is discussed. A threshold-switching curve is achieved using device simulator, results show that this mechanism can explain the threshold-switching phenomenon.

Surface potential is one key variable in DG MOSFET compact modeling. A complete surface potential versus voltage equation and its continuous solution from the accumulation to strong inversion region are presented in this paper for undoped (tightly doped) symmetric double-gate (DG) MOSFETs. The results are based on the exact solution of Poisson's equation with an amending mathematical condition of the continuity, allowing the surface potential to be accurately described from the accumulation region, through sub-threshold, finally to the strong inversion region. From presented surface potential solution, the dependence of the surface potential and corresponding gate capacitance on the quasi-Fermi-potential, silicon film thickness, gate oxide layer, and temperature are tested running different parameters, showing the solution continuity, smoothing, and high accuracy, compared with the 2-D numerical simulation. The presented equation and its solution will be useful in developing a complete surface potential-based DG-MOSFET compact model.

Reliability of FinFETs is studied in this paper using the forward gated-diode generation-recombination (G-R) current. The current-voltage characteristics of a FinFET are measured for parameter extraction and a mathematical algorithm is used to extract the stress-induced interface states and oxide traps of the FinFET from the G-R current measurement. It is observed that the stress-induced interface states and oxide traps can be distinguished by observing the shift of the peak G-R current in the body current (I-b) versus gate voltage (V-g) characteristic. The interface states cause a change in the maximum G-R current (Delta I-peak) while the oxide traps result in a shift of the gate voltage (Delta V-g) corresponding to the Delta I-peak. Unlike bulk MOSFETs, the dominant degradation mechanism of FinFETs is found to be the oxide traps formation rather than the interface states generation.