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A wafer level packaging technique has been developed with an inherent advantage of good solder joint co-planarity suitable for wafer level testing. A suitable weak metallization scheme has also been established for the detachment process. During the fabrication process, the compliancy of the solder joint is enhanced through stretching to achieve a small shape factor. Thermal cycling reliability of these hourglass-shaped, stretch solder interconnections has been found to be considerably better than that of the conventional spherical-shaped solder bumps.

A wafer level packaging technique has been developed with an inherent advantage of excellent solder joint co-planarity essential for wafer level test and burn-in. A suitable weak metallization scheme has also been established for the detachment process. During the fabrication process, the compliancy of the solder joint is enhanced by stretching the solder joint to achieve high aspect ratio and small shape factor. Thermal cycling reliability of these hourglass-shaped, stretch solder joints has been found to be considerably better than that of the conventional spherical-shaped solder bumps.

A cost-effective wafer level packaging technique termed "stretch and break", based on stretching and detachment of solder interconnections, has been established. Excellent co-planarity, essential for wafer level test and burn-in, is inherent in the process. The technique allows the freedom to use solder materials of up to 400/spl deg/C melting temperature for forming the interconnection. The shape of the interconnection can also be easily manipulated for optimum performance. The mechanical and thermal cycling reliabilities of the stretched solder interconnection have been found to be significantly better than those of conventional solder joints.

This paper discusses the effect of board design, the failure mechanism and the board level drop impact performance of two types of common IC packages for hand held electronic product applications namely QFN and CSP, when subjected to the JESD22-B111 test methodology. A method to design test board using low cost 2-layer FR4 material instead of more expensive buildup technologies for board level drop impact test have been developed. Finite element analysis (FEA) of the stress and strain fields during drop impact of the CSP and QFN were performed and verified experimentally. In addition, a cyclic constrained bend test has shown good feasibility to be considered as a simpler alternative assessment of solder joint performance under high strain rate loading.