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For the first time, we report a short channel high performance, gate-all-around strained Si 0.4 Ge 0.6 nanosheet PMOSFET with aggressively scaled dimensions. We demonstrate realization of s-Si 0.4 Ge 0.6 nanosheet with 5nm thickness and device with L G =25nm featuring record high I ON =508 µA/µm at I OFF =100nA/µm and V DS = -0.5V. This result is obtained with the combination of (a) novel Si-cap-free gate oxide solution featuring thin EOT=9.1A, low D IT and N IT for s-Si 0.4 Ge 0.6 channel, (b) record high hole mobility= 450 cm2/Vs owing to compressive strain imparted by Si 0.7 Ge 0.3 strain relaxed buffer (SRB), (c) low R EXT =150 Ω-µm due to highly active, strained source/drain SiGe process and novel p++ cap layer, (d) optimized source/drain tip and junction to minimize GIDL impact to I OFF . Additionally, the impact of operating temperature on GIDL and I OFF is comprehensively studied to prescribe optimal V CC range of operation for this technology.

We demonstrate 3-D self-aligned stacked NMOS-on-PMOS multiple Si nanoribbon transistors with successful integration of vertically stacked dual source/drain EPI process and vertically stacked dual metal gate process. Both top NMOS and bottom PMOS show high on-state performance and superior short channel control. A functional CMOS inverter is also demonstrated with well-balanced voltage transfer characteristics. The 3-D self-aligned stacked CMOS nanoribbon transistor is demonstrated as a promising transistor architecture to continue Moore’s law scaling.

We expand on our work in [1] by demonstrating both Si P- and NMOS finfet transistors monolithically integrated with GaN transistors on 300mm Si(111) wafers using 3D integration. With the Si finfet architecture, we are able to take advantage of the fin orientations of the transferred Si(100) crystal to fabricate both high performance Si P- and NMOS transistors. Furthermore, we demonstrate a variety of GaN transistor innovations, including enhancement (e-mode) and depletion mode (d-mode) GaN NMOS transistor with high $\mathrm{I}_{\mathrm{D}}=1.8\mathrm{m}_{1}\mathrm{W}\mu \mathrm{m};\mathrm{GaN}$ Schottky gate transistor producing high saturated power of 20dBm with peak PAE=57% at 28GHz; high performing, low leakage cascode and multi-gate GaN transistors; and GaN Schottky diodes with ultra-low $\mathrm{C}_{\mathrm{OFF}}$ for ESD protection, all integrated on 300mm Si(111) wafer.

We report a short channel high performance Ge PMOS integrated with Si NMOS in sequential monolithic 3D stacking. A layer transfer Ge PMOS with record I ON = 497 μA/μm at I OFF = 8nA/μm and I ON = 630 μA/μm at I OFF = 100nA/μm and V DS = -0.5V is achieved for the first time. Optimized design of metal gate and contact on bottom Si NMOS device layer, along with a low process thermal budget developed for Ge layer transfer and top Ge PMOS device fabrication, allow for sequential stacking with no degradation on each MOS device characteristics. Heterogeneous 3D stacked Ge-Si CMOS inverter is also successfully demonstrated with drive performance maintained on Ge PMOS and Si NMOS.

We have demonstrated industry’s first 300mm 3D heterogeneous integration of high performance, low-leakage high-K dielectric metal gate enhancement-mode (e-mode) GaN NMOS and Si PMOS transistors on 300mm high-resistivity (HR) Si(111) substrate, enabled by 300mm GaN MOCVD epitaxy and 300mm 3D layer transfer. The fabricated (bottom device layer) high-K dielectric e-mode GaN NMOS transistors, integrated on a 300mm HR Si(111) substrate, show excellent electrical characteristics and figure-of-merits (FOM) for realizing energy-efficient, compact voltage regulators and RF front-end components such as power amplifiers, low-noise amplifiers and RF switches, with (i) I OFF as low as 100pA/μm (V D =5V, V G =0V), (ii) high I D,max =1.5mA/μm; (iii) R ON as low as 610Ω-μm, significantly better than industry-standard Si transistors at equivalent drain breakdown (BV D ), (iv) excellent RF performance: f T =190GHz, f MAX =300GHz, PAE=56% at mmwave frequency (f=28GHz), and PAE=70% at sub-7GHz (f=5GHz), significantly better than industry-standard GaAs and Si RF transistors, (v) excellent RF switch FOM, R on C off =110fs, and (vi) low noise figure, NF min =1.36dB (f=28GHz), 0.4dB (f=5GHz) and 0.27dB (f=1.8GHz), all at SoC-compatible voltages. The fabricated (top device layer) L G =65nm and 130nm Si PMOS transistors, which are monolithically integrated on top of the bottom GaN NMOS transistors by 300mm 3D layer transfer, show respectively, high drive current of 0.85mA/μm, and low I off of 150pA/μm at V D =-1.2V. Such a monolithic 3D integration of GaN NMOS and Si PMOS enables full integration of energy-efficient, truly compact power delivery and RF solutions with CMOS digital signal processing, logic computation and control, memory functions and analog circuitries for next generation power delivery, RF (5G and beyond) and SoC applications.

In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and scaled gate-to-source/gate-to-drain (L SIDE ) have been fabricated and compared. For the first time, 3-D Tri-gate InGaAs devices demonstrate electrostatics improvement over the ultra-thin (QW thickness, T QW =10nm) body planar InGaAs device due to (i) narrow fin width (W FIN ) of 30nm and (ii) high quality high-K gate dielectric interface on the InGaAs fin. Additionally, the 3-D Tri-gate InGaAs devices in this work achieve the best electrostatics, as evidenced by the steepest SS and the smallest DIBL, ever reported for any high-K III–V field effect transistor. The results in this work show that the 3-D Tri-gate device architecture is an effective way to improve the scalability of III–V FETs for future low power logic applications.

In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (L SIDE ) of 5nm are reported for the first time. The high-K gate dielectric formed on this non-planar device structure has the expected thin TOXE of 20.5A with low J G , and high quality gate dielectric interface. The simplified S/D scheme is needed for the non-planar architecture while achieving significant reduction in parasitic resistance. Compared to the planar high-K InGaAs QWFET with similar T OXE , the non-planar, multi-gate InGaAs QWFET shows significantly improved electrostatics due to better gate control. The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III–V QWFETs for low power logic applications.

This paper describes integration of an advanced composite high-K gate stack (4nm TaSiO x -2nm InP) in the In 0.7 Ga 0.3 As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (t OXE ) and low gate leakage (J G ) and (ii) effective carrier confinement and high effective carrier velocity (V eff ) in the QW channel. The L G =75nm In 0.7 Ga 0.3 As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750µS/µm and high drive current of 0.49mA/µm at V DS =0.5V.

In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and substrate injection effects. Processing conditions were optimized to achieve comparable TDDB lifetimes on HK+MG structures at 30% higher E-fields than SiON with a reduction in SILC growth. Extensive long-term stress data collection results and a change in voltage acceleration are reported.

This paper describes for the first time, the heterogeneous integration of In0.7Ga0.3As quantum well device structure on Si substrate through a novel, thin composite metamorphic buffer architecture with the total composite buffer thickness successfully scaled down to 1.mum, resulting in high- performance short-channel enhancement-mode In0.7Ga0.3As QWFETs on Si substrate for future high-speed digital logic applications at low supply voltage such as 0.5 V.