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In this paper, we report the analysis, design, and implementation of stacked transistors for power amplifiers realized on InP Double Heterojunction Bipolar Transistors (DHBTs) technology. A theoretical analysis based on the interstage matching between all the single transistors has been developed starting from the small-signal equivalent circuit. The analysis has been extended by including large-signal effects and layout-related limitations. An evaluation of the maximum number of transistors for positive incremental power and gain is also carried out. To validate the analysis, E-band three- and four-stacked InP DHBT matched power cells have been realized for the first time as monolithic microwave integrated circuits (MMICs). For the three-stacked transistor, a small-signal gain of 8.3 dB, a saturated output power of 15 dBm, and a peak power added efficiency (PAE) of 5.2% have been obtained at 81 GHz. At the same frequency, the four-stacked transistor achieves a small-signal gain of 11.5 dB, a saturated output power of 14.9 dBm and a peak PAE of 3.8%. A four-way combined three-stacked MMIC power amplifier has been implemented as well. It exhibits a linear gain of 8.1 dB, a saturated output power higher than 18 dBm, and a PAE higher than 3% at 84 GHz.

An InP Double Heterojunction Bipolar Transistor (DHBT) technology is presented for millimeter-wave power amplifiers at E-band and higher frequencies. Single- and multi-finger transistors with 0.7m emitter width and emitter lengths of 5, 7, 10m are designed for high frequency and high power applications. The static and AC performances of the fabricated devices are discussed. Reported cutoff frequency and maximum oscillation frequency are ft=267GHz and fmax=450GHz for a 0.75mP2 single-finger device, respectively. Results from large-signal measurements at 30GHz are reported for single and 4-finger devices. Ballasted devices are introduced to improve thermal behaviour and to increase the limits of the safe operating area (SOA). The SOA is improved approximately by 75% for 4-finger devices with 0.710m2 emitter. A fabricated monolithic microwave integrated circuit (MMIC) at E-band based on stacked InP DHBTs is presented and its performances reported to demonstrate the power capabilities of the technology.

A novel millimeter-wave ballasted stacked-transistor configuration implemented on a 0.7 μm InP double heterojunction bipolar transistor (DHBT) process is proposed in this paper. A ballasting resistive network connected to the emitter leads of the common-base stage proves to be very effective in extending the safe operating area (SOA) of a unit power cell. Electromagnetic-circuit co-simulations based on a DHBT large-signal model including thermal effects show a significant increase of the attainable voltage swing under RF operation. Experimental results at E-band obtained from a two-stage monolithic microwave integrated circuit (MMIC) power amplifier validate the analysis and design. A small-signal gain of 13.9 dB at 71 GHz and an output power higher than 17.3dBm at 75 GHz have been observed experimentally on the fabricated MMIC.

In this paper we present the design and measurements of a two-stage 75-GHz InP Double Heterojunction Bipolar Transistor (DHBT) power amplifier (PA). An optimized two-stacked transistor power cell has been designed, which represents the building block in the power stage as well as in the driver stage of the power amplifier. Besides the series voltage addition of the stacked structure, parallel power combining techniques were adopted to increase the output power of the MMIC amplifier, with four-way and eight-way corporate power combiners at the driver and power stages, respectively. At 75 GHz, the power amplifier exhibits a small signal gain of G = 12.6 dB, output power at 1-dB compression of P out, 1dB = 18.6 dBm and a saturated output power of P sat > 21.4 dBm.

This work presents the design of a planar ultra-wideband (UWB) four-way power divider/combiner. A prototype has been fabricated on a printed circuit board and characterized. For achieving the frequency response required in UWB applications, each branch of the divider is conceived as a three-section Chebyshev impedance transformer. The defected ground structure (DGS) technique has been used to obtain the required high impedance lines. The power divider's insertion loss is 1 dB at 3.1 GHz and 2.9 dB at 10 GHz; the input reflection is lower than −10 dB, and the isolation between the output ports is better than 13 dB from 3 GHz to 10 GHz. A back-to-back configuration has been implemented as well. Its insertion loss is lower than 5 dB and its input reflection is lower than −10 dB over the UWB frequency range.

This paper presents the comparison between the simulated and measured thermal resistance of InP Double Heterojunction Bipolar Transistors (DHBT). 3D thermal simulations were carried out in order to compute the temperature distribution across the full structure due to a constant power excitation of devices with up to 8 emitter fingers. The surface temperature profile was then used to compute the average thermal resistance of the multi-finger devices. The comparison with the corresponding results obtained by electrical measurements show a good agreement. The temperature profiles from several simulations are used to extract the thermal resistance matrix used in the electro-thermal coupling network of a compact large-signal model.

A large-signal modeling approach has been developed for multi-finger devices fabricated in an Indium Phosphide (InP) Double Heterojunction Bipolar Transistor (DHBT) process. The approach utilizes unit-finger device models embedded in a multi-port parasitic network. The unit-finger model is based on an improved UCSD HBT model formulation avoiding an erroneous RciCbci transit-time contribution from the intrinsic collector region as found in other III-V based HBT models. The mutual heating between fingers is modeled by a thermal coupling network with parameters extracted from electro-thermal simulations. The multi-finger modeling approach is verified against measurements on an 84 GHz power amplifier utilizing four finger InP DHBTs in a stacked configuration.

An Indium Phosphide (InP) Double Heterojunction Bipolar Transistor (DHBT) process has been utilized to design two doublers to cover the 94 GHz and 188 GHz bands. The 94 GHz doubler employs 4-finger DHBTs and provides conversion loss of 2 dB. A maximum output power of nearly 3 dBm is measured while the doubler is not entirely saturated. The DC power consumption is 132 mW. The 188 GHz doubler utilizes a 1-finger DHBT. Conversion loss of 2 dB and a maximum output power of −1 dBm are achieved at 188 GHz with on-wafer measurements. The DC power consumption is 24 mW under saturated conditions. Both doublers operate over a broad bandwidth. The total circuit area of each chip is 1.41 mm2.

Multifinger InP DHBTs can be designed with a ballasting resistor to improve power capability. However accurate modeling is needed to predict high frequency behavior of the device. This paper presents two distinct modeling approaches: one based on EM simulations and one based on a physical equivalent circuit description. In the first approach, the EM simulations of contact pads and ballasting network are combined with the small-signal model of the intrinsic device. In the second approach, the ballasting network is modeled with lumped components derived from physical analysis of the layout and then combined with EM simulated contact pads and with the device model. The models are validated against S-parameters measurements of real devices up to 65 GHz showing good agreement in terms of maximum available gain. In addition, a MAG of 2–4 dB at 170 GHz shows that ballasted devices can be employed for power amplifiers in D band.

This paper presents the characterization of single and multi-finger Indium Phosphide Double Heterojunction Bipolar transistors (InP DHBTs). It is used as the starting point for technology optimization. Safe Operating Area (SOA) and small signal AC parameters are investigated along with thermal characteristics. The results are presented comparing different device dimensions and number of fingers. This work gives directions towards further optimization of geometrical parameters and reduction of thermal effects.