Optimization of InP DHBT stacked-transistors for millimeter-wave power amplifiers

In this paper, we report the analysis, design, and implementation of stacked transistors for power amplifiers realized on InP Double Heterojunction Bipolar Transistors (DHBTs) technology. A theoretical analysis based on the interstage matching between all the single transistors has been developed starting from the small-signal equivalent circuit. The analysis has been extended by including large-signal effects and layout-related limitations. An evaluation of the maximum number of transistors for positive incremental power and gain is also carried out. To validate the analysis, E-band three- and four-stacked InP DHBT matched power cells have been realized for the first time as monolithic microwave integrated circuits (MMICs). For the three-stacked transistor, a small-signal gain of 8.3 dB, a saturated output power of 15 dBm, and a peak power added efficiency (PAE) of 5.2% have been obtained at 81 GHz. At the same frequency, the four-stacked transistor achieves a small-signal gain of 11.5 dB, a saturated output power of 14.9 dBm and a peak PAE of 3.8%. A four-way combined three-stacked MMIC power amplifier has been implemented as well. It exhibits a linear gain of 8.1 dB, a saturated output power higher than 18 dBm, and a PAE higher than 3% at 84 GHz.