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International audience; In this paper we present a full free addressable 4kb EEPROM memory array. This test structure based on CAST vehicle has been upgraded with flexible addressing logic to select any numbers of cells on single or multiple word lines. To this aim, column/row shift registers, to enable an easy cell biasing, have been implemented in an embedded non-volatile memory environment. High voltage circuits, driven by low voltage shift registers, are used to bias selected cells for electrical characterizations and reliability tests purposes. This kind of structure has been developed to improve the efficiency of electrical characterization laboratory, resulting in an enhanced acquisition with respect to standard CAST test techniques, opening the path to fine statistical analysis.

International audience; In this paper, we present an experimental study of a new architecture of the embedded Select in Trench Memory (eSTM™) cell. A first part is dedicated to a deep analysis of the overlap eSTM TM behaviour. A key fact is the possibility to achieve a large programming window thanks to tip effect enhanced erase. After the study on erase operation scheme, we demonstrate the impact of Select to Floating gate tip coupling on the endurance results. The endurance results are thus improved up to 500k cycles using the overlap eSTM TM .

International audience; A novel True Random Number Generator circuit fabricated in a 130nm HfO2-based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the proposed programming scheme, all the cells of the memory array are addressed at the same time while the current provided to the circuit is limited to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values. Some cells are switched in a low resistive state, other cells are slightly programmed to reach an intermediate resistance state, while the remaining cells maintain their initial high resistance state. Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks. The generated random bit stream has successfully passed twelve NIST tests out of fifteen. Compared to state-of-the-art resistive RAM-based true random number generators, our proposed methodology is the first one to leverage on programming current limitation at a memory array level.

International audience; A novel True Random Number Generator circuit fabricated in a 130nm HfO2-based resistive RAM process is presented. The generation of the random bit stream is based on a specific programming sequence applied to a dedicated memory array. In the proposed programming scheme, the voltage applied to the cells of the memory array is fixed at the median SET voltage of the distribution, to program only a subset of the memory array, resulting in a stochastic distribution of cell resistance values. Some cells are switched in a low resistive state, while the remaining cells maintain their initial high resistance state. Resistance values are next converted into a bit stream and confronted to National Institute of Standards and Technology (NIST) test benchmarks. The generated random bit stream has successfully passed eleven NIST tests out of fifteen without any post-processing.

International audience; In this paper, a new device architecture has been studied by TCAD process simulations in order to provide the improvements on the electrical characteristics. We focus mainly on the drain-bulk junction breakdown voltage, of a double 130 nm poly gate transistor for Non-Volatile Memory technology. It is used as a word line select transistor, handling the drain voltage up to 13 V. The proposed structure has been implemented on silicon and the electrical measurements demonstrate the good predictability given by simulations. Finally, a new zero-cost added process asymmetric architecture is also studied to propose further improvements in terms of footprint or electrical characteristics.

The behaviour of semiconductor materials and devices subjected to femtosecond laser irradiation has been under scrutiny, for many reasons, during the last decade. In particular, recent works have shown that the specific functionality and/or geometry of semiconductor devices, among which non-volatile memory (NVM) devices hold a special place, could be used to improve the knowledge about ultrafast laser-semiconductor interactions. So far, such an approach has been applied to draw conclusions about the spatio-temporal properties of laser propagation in bulk materials. Here, by comparing the evolution of the electrical characteristics of Flash cells under the cumulative effect of repeated femtosecond laser pulses with first-order physical considerations and TCAD (Technology Computer Aided Design) simulations, we clearly establish the role of the carriers created by nonlinear ionization on the functionality of the structures. The complete electrical analysis informs indirectly on the energy of the laser-produced free-carriers which, to date, was almost inaccessible by an experimental method applicable to the bulk of a material. Establishing the link between the carrier energy and laser parameters is of major importance to improve the comprehension of the nonlinear ionization mechanisms associated to intense laser-semiconductor interactions and applied in various fields from microelectronics to laser micromachining.

We perform experiments and device simulations to investigate the origin of current-voltage (I-V) linearity of TaOX-based resistive switching memory (RRAM) devices for their possible application as electronic synapses. By using electrical characterization and simulations, we link the electrical characteristics (linear or nonlinear I-V) to the microscopic properties of the conductive filament (CF). Our findings indicate that the shape and the thermal properties of the CF region are crucial to achieve linear I-V characteristics. These results allow optimizing the I-V curve linearity of TaOX-based RRAM devices, explaining the wide range of linear I-V characteristics experimentally observed on RRAM device obtained. When weight sum operation using SPICE simulations is performed, the read current is improved under the condition of linear I-V characteristics due to current loss minimization.

International audience; In this paper, a new continuous multilevel compact model for phase-change memory (PCM) is proposed. It is based on modified rate equations with the introduction of a variable related to GST melting. The model is evaluated using a large set of dynamic measurements and shows a good accuracy with a single model card. All fitting parameters are discussed and their impacts are detailed. Full circuit simulation is performed. Good convergence and fast simulation time suggest that this new compact model can be exploited for PCM circuit design.

International audience; This paper presents a new diode selector for embedded Phase Cahnge Memory (PCM) in advanced FD-SOI technology. It has been developed to achieve a very low cost selector device but still very efficient to meet PCM specifications. This new device takes advantages of CMOS in FD-SOI: buried oxide (BOX), shallow trench isolation (STI) and high k metal gates allow very low leakages between cells, thus offering great potential for designing embedded memory arrays of up to several Mbit. The selector can drive 300μA at 2V through the memory cell with 2.5V applied on gates together with a limited leakage current of less than 10pA/cell. The effective cell area of under 0.025μm 2 is very competitive as compared to a MOS selector, offering a size reduction of around 60% for the same drinving current. Therefore, the new diode on FD-SOI devices is a great solution for a PCM selector due to its low cost and high density.

The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress.

International audience; We demonstrate that infrared femtosecond laser pulses with intensity above two-photon ionization threshold of crystalline silicon (c-Si) induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor (MOS) transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, defectivity) and for new developments in the growing field of ultrafast microelectronics. The interaction between focused infrared femtosecond laser pulses and bulk crystalline silicon (c-Si) results in the formation of microplasmas 1 by multiphoton ionization. 2, 3 Thereby, one could expect to reach the critical electron density of c-Si by simply increasing the laser intensity. However, a recent theoretical study has demonstrated that this density cannot be reached with femtosecond laser irradiation due to plasma defocusing phenomenon which prevents the material from any permanent modification. 4 It is thus natural to investigate the possibility to handle the free-carriers produced in this regime of self-limited excitation. The most likely field where such a study can be applied is microelectronics. In this context, several studies have been conducted during the last decade on laser-transistor interactions. 5-7 Although these works have shown an impact of the laser on the device, irradiations at 1064 nm were involved implying only modest free-carrier production (ionization) at the transistor region. To solve this issue, El-Mamouni et al. employed a longer wavelength performing laser experiments relying on localized two-photon ionization on fin field-effect transistors (FinFETs). 8 Due to the nonlinear nature of the ionization of c-Si by photons with sub-bandgap energy, the volume of the subsequent plasma is extremely confined with a high electron density. Nevertheless, FinFETs are multigate structures making difficult the evaluation of the laser effect on each gate individually. Among all the existing microelectronic devices, one of the most relevant that is able to store laser-produced free-carriers is the Flash memory due to the possibility to evaluate the number of carriers trapped inside the floating gate (FG) of the device. 9-11 This latter is the place where electrons can be stocked, defining the logical state of the memory. When no charge is stored in the FG, the particular value of the threshold voltage () of the Flash cell is called the neutral threshold voltage (0). This state used to be reached after ultraviolet (UV) frontside exposure imparting to electrons sufficient energy to migrate inside or outside the floating gate. 12 However, this technique is not applicable anymore for advanced technologies because the stacks of metal used for electrical circuitry prevent UV penetration. Since the knowledge of 0 is crucial for the characterization and the reliability assessment of Flash memories, 13 the elaboration of a nondestructive, rapid and contactless experimental method for determining this parameter is essential.

The development of new wireless devices is growing up, driven by the market of connected things for many applications: communications, cloud and health. In this scenario the current consumption of memory devices plays a key role. To save the battery of these devices, we need to develop the components that consume less and less. In this paper we propose to improve the performances of an original architecture of nonvolatile memory cell: the Asymmetrical Tunnel Window (ATW) cell. We compare here the standard Flash floating gate memory cell with the new proposed device, with an accurate experimental investigation of programming window and energy consumption. Moreover we optimized the ATW cell architecture by modifying the ratio of oxides lengths and thicknesses. Finally, we experimentally demonstrate an improvement of 4 times on the programming efficiency with respect the standard memory.

International audience; In this paper we present the last improvement on programming window and consumption of silicon nanocrystal memory cell (Si-nc). Using a dynamic technique to measure the drain current during the hot carrier injection (HCI) programming operation, we explain the behavior of Flash floating gate (F.G.) and silicon nanocrystal memories. We use TCAD simulations to reproduce the charge diffusion in the nanocrystal trapping layer in order to understand the physical mechanism. Finally experimental results of electrical characterizations are shown using different bias conditions to compare the devices.

International audience; The microelectronic industry requires more and more low consumption and high reliability solutions. In this scenario the silicon nanocrystal memories (Si-nc) are one of the most mature technologies able to replace the Flash floating gate in NOR embedded applications. The main advantages of Si-nc memories are: the full compatibility with the CMOS process using a reduced number of masks (1) and the robustness against SILC (2). In this paper we present an experimental work on the optimized silicon nanocrystal cell industrially manufactured, where the reliability is improved (3). In particular the impact of silicon nanocrystals size and temperature on cell programming window is shown. Moreover we demonstrated for the first time at our knowledge that it is possible to achieve 1Mcycles endurance characteristic in the temperature range of [-40°C; 150°C], programming by channel hot electron (CHE) and erasing by Fowler-Nordheim (FN). Technical Details The Non-Volatile Memories (NVM) integrating silicon nanocrystals are considered as an emerging solution to extend Flash memories downscaling. In this paragraph we explain the Si-nc industrial nucleation and grown fabrication process by Low Pressure Chemical Vapor Deposition (LPCVD). In a context of technological industrialization, it is of primary importance to develop in-line metrology tools dedicated to Si-nc growth process control. Hence, silicon nanocrystals were observed in top view by using an in-line Critical Dimension Scanning Electron Microscopy (CDSEM), thus their average size and density were extracted from image processing (4). Silicon nanocrystal fabrication process Silicon nanocrystals were grown on top of a thin silicon oxide (SiO 2) by Low Pressure Chemical Vapor Deposition two steps recipe. The active tunnel oxide surface was chemically prepared to increase the number of silanol groups which are used as nucleation sites; this cleaning step impacts the final tunnel oxide thickness (5). SiO 2 top surface presents both siloxane (Figure 1a) and silanol (Figure 1b) units. The two steps process was used in either epitaxy tool or in industrial LPCVD furnace. The first step consists in nucleation with silane (SiH 4) diffusion on hydroxyl tunnel oxide surface (Figure 1c). The second step concerns a selective growth achieved by using

In this paper we investigate the energy consumption of Discrete-Trap Silicon Nanocrystal (Si-nc) Nonvolatile Memory Cell during Channel Hot Electron programming operation. We compare this cell with a Floating Gate Flash in order to evaluate the current absorption and the energy consumption under different conditions. Using a commercial TCAD simulator, a good agreement between data and simulations is obtained and the involved mechanisms are analysed. Then we propose a solution to optimize the programming window and energy consumption trade-off for Si-nc Flash Cells.

In this paper we report results on PCM endurance failure characterization. We show that endurance failure is related to SET pulse features and we analyze and model SET operation to obtain a better understanding and improve endurance performance. Results give interesting insights on the crystallization process of GST material. SET obeys to a constant energy law. Fast SET pulses require high power; slow SET pulses can be implemented in low power applications. Results may be used for optimized SET/RESET operation to achieve better endurance.

Alumina is a key material for developing innovative Charge-Trapping Non-Volatile Memory (CT-NVM) devices. Al 2 O 3 is used to implement the top dielectric in TANOS devices [1], and it has been proposed as trapping layer [2] and to engineer the tunnel dielectric [3]. Despite the large use of this material, the quantitative investigation of defect features still lacks. In this scenario, the purpose of this work is to investigate the physics of electron/hole trapping/detrapping mechanisms in Al 2 O 3 . Combining I-V and C-V measurements with a physical model we derive the energy levels of electron/hole traps and the location of electron/hole charge. The influence of electron/hole alumina traps on TANOS operations and reliability is investigated.

We investigate the electron/hole trapping phenomena in alumina blocking oxide and their impact on the program/erase operations and retention of TaN/Al2O3/Si3N4/SiO2/Si (TANOS) memory devices. For this purpose, we perform simulations using a physical model that reproduces the charge injection/trapping in TANOS devices, which is extended in order to account for the charge trapping phenomena in the blocking layer. We derive the electrical characteristics of both electron and hole traps in Al2O3 by reproducing the measured program, erase, and retention transients. Our results show that the amount of electron charge trapped in the alumina during a program operation strongly depends on the stack composition and program voltages and can account for up to 25% of the total threshold voltage shift, whereas hole trapping during erase is negligible. Finally, we investigate the degradation of retention caused by the electron trapping in the alumina blocking layer, which is shown to result in an accelerated charge loss.

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We present a detailed investigation of temperature effects on the operation of TaN/Al2O3/Si3N4/SiO2/Si (TANOS) memory devices. We show that not only retention but also program and erase operations are affected significantly by temperature. Using a large set of experimental data and simulations on a variety of TANOS stacks, we show that the temperature dependence of TANOS program and erase operations can be explained by accounting for that the alumina dielectric constant increases by 20%–25% over a 125 K temperature range.