77 results on '"Velenis, D."'
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2. (Why do we need) Wireless Heterogeneous Integration (anyway?)
3. Cost-effective RF interposer platform on low-resistivity Si enabling heterogeneous integration opportunities for beyond 5G
4. Characterization of Impact of Vertical Stress on FinFETs
5. TSV-assisted Hybrid FinFET CMOS - Silicon Photonics Technology for High Density Optical I/O
6. In-situ Investigation of the Impact of Externally Applied Vertical Stress on III-V Bipolar Transistor
7. High-Speed TSV Integration in an Active Silicon Photonics Interposer Platform
8. Hybrid 14nm FinFET - Silicon Photonics Technology for Low-Power Tb/s/mm2 Optical I/O
9. Optimal yaw-rate target for electric vehicle torque vectoring system
10. Processing active devices on Si interposer and impact on cost
11. Active-lite interposer for 2.5 & 3D integration
12. Active-lite interposer for 2.5 & 3D integration
13. Demonstration of a cost effective Cu electroless TSV metallization scheme
14. Semi-additive Cu-polymer RDL process for interposers applications
15. Process development to enable 3D IC multi-tier die bond for 20μM pitch and beyond
16. Wafer thinning and back side processing to enable 3D stacking
17. Test Structures for Characterization of Through-Silicon Vias
18. Challenges and improvements for 3D-IC integration using ultra thin (25μm) devices
19. Electrical characterization method to study barrier integrity in 3D through-silicon vias
20. 3D stacking using ultra thin dies
21. Imec silicon photonics platforms: performance overview and roadmap
22. Development of cost-effective biocompatible packaging for microelectronic devices
23. Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers
24. Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance
25. Temperature dependent electrical characteristics of through-si-via (TSV) interconnections
26. Session details: CAD for embedded systems
27. Block placement for reduced delay uncertainty in high performance clock distribution networks
28. Effects of parameter variations and crosstalk on H-tree clock distribution networks
29. 3D stacking using ultra thin dies.
30. Cost effectiveness of 3D integration options.
31. An IC-centric biocompatible chip encapsulation fabrication process.
32. On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking.
33. Impact of 3D design choices on manufacturing cost.
34. Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees.
35. Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees.
36. DEMONSTRATION OF SPEED AND POWER ENHANCEMENTS ON AN INDUSTRIAL CIRCUIT THROUGH APPLICATION OF CLOCK SKEW SCHEDULING
37. Buffer sizing for delay uncertainty induced by process variations.
38. Demonstration of power enhancements on an industrial circuit through delay management of non-critical data paths.
39. Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C–V Technique.
40. Effects of Parameter Variations on Low-Power SRAM Decoder.
41. Thermal stability of copper Through-Silicon Via barriers during IC processing.
42. Temperature dependent electrical characteristics of through-si-via (TSV) interconnections.
43. Active-lite interposer for 2.5 & 3D integration.
44. Reduced delay uncertainty in high performance clock distribution networks
45. Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling
46. Power Supply Variation Effects on Timing Characteristics of Clocked Registers
47. Demonstration of power enhancements on an industrial circuit through delay management of non-critical data paths
48. A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty
49. Buffer sizing for delay uncertainty induced by process variations
50. Effects of crosstalk noise on H-tree clock distribution networks
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