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Importance There is a major need for effective, well-tolerated treatments for idiopathic pulmonary fibrosis (IPF). Objective To assess the efficacy and safety of the autotaxin inhibitor ziritaxestat in patients with IPF. Design, Setting, and Participants The 2 identically designed, phase 3, randomized clinical trials, ISABELA 1 and ISABELA 2, were conducted in Africa, Asia-Pacific region, Europe, Latin America, the Middle East, and North America (26 countries). A total of 1306 patients with IPF were randomized (525 patients at 106 sites in ISABELA 1 and 781 patients at 121 sites in ISABELA 2). Enrollment began in November 2018 in both trials and follow-up was completed early due to study termination on April 12, 2021, for ISABELA 1 and on March 30, 2021, for ISABELA 2. Interventions Patients were randomized 1:1:1 to receive 600 mg of oral ziritaxestat, 200 mg of ziritaxestat, or placebo once daily in addition to local standard of care (pirfenidone, nintedanib, or neither) for at least 52 weeks. Main Outcomes and Measures The primary outcome was the annual rate of decline for forced vital capacity (FVC) at week 52. The key secondary outcomes were disease progression, time to first respiratory-related hospitalization, and change from baseline in St George’s Respiratory Questionnaire total score (range, 0 to 100; higher scores indicate poorer health-related quality of life). Results At the time of study termination, 525 patients were randomized in ISABELA 1 and 781 patients in ISABELA 2 (mean age: 70.0 [SD, 7.2] years in ISABELA 1 and 69.8 [SD, 7.1] years in ISABELA 2; male: 82.4% and 81.2%, respectively). The trials were terminated early after an independent data and safety monitoring committee concluded that the benefit to risk profile of ziritaxestat no longer supported their continuation. Ziritaxestat did not improve the annual rate of FVC decline vs placebo in either study. In ISABELA 1, the least-squares mean annual rate of FVC decline was –124.6 mL (95% CI, −178.0 to −71.2 mL) with 600 mg of ziritaxestat vs –147.3 mL (95% CI, −199.8 to −94.7 mL) with placebo (between-group difference, 22.7 mL [95% CI, −52.3 to 97.6 mL]), and –173.9 mL (95% CI, −225.7 to −122.2 mL) with 200 mg of ziritaxestat (between-group difference vs placebo, −26.7 mL [95% CI, −100.5 to 47.1 mL]). In ISABELA 2, the least-squares mean annual rate of FVC decline was –173.8 mL (95% CI, −209.2 to −138.4 mL) with 600 mg of ziritaxestat vs –176.6 mL (95% CI, −211.4 to −141.8 mL) with placebo (between-group difference, 2.8 mL [95% CI, −46.9 to 52.4 mL]) and –174.9 mL (95% CI, −209.5 to −140.2 mL) with 200 mg of ziritaxestat (between-group difference vs placebo, 1.7 mL [95% CI, −47.4 to 50.8 mL]). There was no benefit with ziritaxestat vs placebo for the key secondary outcomes. In ISABELA 1, all-cause mortality was 8.0% with 600 mg of ziritaxestat, 4.6% with 200 mg of ziritaxestat, and 6.3% with placebo; in ISABELA 2, it was 9.3% with 600 mg of ziritaxestat, 8.5% with 200 mg of ziritaxestat, and 4.7% with placebo. Conclusions and Relevance Ziritaxestat did not improve clinical outcomes compared with placebo in patients with IPF receiving standard of care treatment with pirfenidone or nintedanib or in those not receiving standard of care treatment. Trial Registration ClinicalTrials.gov Identifiers: NCT03711162 and NCT03733444

Time dependent dielectric breakdown (TDDB) reliability is studied on interfacial layer (IL)/high-K gate stack of Gate-All-Around Nanosheet (GAA-NS) N- and P-type Field Effect Transistors (FETs) with volume-less multiple threshold voltage (multi-Vt) integration scheme enabled by the dual dipoles (n-dipole and p-dipole). We report for the first time Key TDDB Modeling parameters: voltage acceleration exponent (VAE), Weibull slope ( $\beta$ ), and activation energy (E a ) and show robust TDDB reliability in multi-Vt NS transistors enabled by different dipoles.

Over the past several years, stacked Nanosheet Gate-All-Around (GAA) transistors captured the focus of the semiconductor industry and has been identified as the new lead architecture to continue LOGIC CMOS scaling beyond-5nm node. The fabrication of GAA devices requires new specific integration modules. From very early processing points, these structures require complex metrology to fully characterize the three-dimensional parameter set. As the technology continues through research and development cycles and looks to transition to manufacturing, there are many opportunities and challenges remaining for inline metrology. Especially valuable are measurement techniques which are non-destructive, fast, and provide multi-dimensional feedback, where reducing dependencies on offline techniques has a direct impact to the frequency of cycles of learning. More than previous nodes, then, this node may be when some of these offline techniques jump from the lab to the fab, as certain critical measurements need to be monitored realtime. Thanks to the compute revolution this very industry enabled, machine learning has begun to permeate inline disposition, and hybrid metrology systems continue to advance. Metrology solutions and methodologies developed for prior technologies will also still have a large role in the characterization of these structures, as effects such as line edge roughness (LER), pitchwalk, and defectivity continue to be managed. This paper reviews related prior studies and advocates for future metrology development that ensures nanosheet technology has the inline data necessary for success.

Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet technology in the FEOL. While sheet and gate pitches expected for the beyond 7nm node fall within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet device performance requirements at technology critical sheet widths and gate lengths. Here, we demonstrate electrical performance of nanosheet FET’s with 20 – 80 nm wide sheets with 40-150 nm pitch gates patterned with single expose EUV. We compare results against a benchmark double patterning process towards meeting variability, device and critical dimension targets. We also explore the limits of process and material knobs - resists, illuminations and etch chemistries with the specific goal of reducing LER/LWR and towards shrink for further scaling. Our results demonstrate crossover points between direct print EUV and double patterning processes for nanosheet technology and identify relevant design guidelines and focus areas to successfully enable EUV for the FEOL in nanosheets.

Interstitial lung disease (ILD) is a common manifestation of systemic sclerosis and a leading cause of systemic sclerosis-related death. Nintedanib, a tyrosine kinase inhibitor, has been shown to have antifibrotic and antiinflammatory effects in preclinical models of systemic sclerosis and ILD., info:eu-repo/semantics/published

An analysis of NanoSheet (NS) transistor parasitic resistance components is presented and correlated to the resistance readout on Si wafers. With this model, it is possible to identify which components cause the parasitic resistance increases as CPP (contacted poly-Si pitch) further scales from 48 nm to 44 nm pitch. In this study, an alternative MOL (middle of line) metallization scheme is implemented to reduce circuit RC delay. This model helps to further reduce the transistor parasitic resistance from NFET/PFET S/D (source/drain) epitaxy or silicide. As CPP scales, NS PFET parasitic resistance reduction is more challenging and requires optimization in S/D epitaxy, silicide and metallization. Based on parasitic resistance modeling, we present a new wrap-around contact structure which eliminates the vertical epi resistance component, hence reducing overall device resistance.

The methodology of measuring the lateral etch, or indentation, of SiGe nanosheets by using optical scatterometry, x-ray fluorescence, and machine learning algorithms is presented and discussed. Stacked nanosheet device structures were fabricated with different etch conditions in order to induce variations in the indent. It was found that both scatterometry in conjunction with Spectral Interferometry and novel interpretation algorithms as well as TEM calibrated LE-XRF are suitable techniques to quantify the indent. Machine learning algorithms enabled an additional solution path by combining LE-XRF data with scatterometry spectra therefore avoiding the need for a full optical model.

For stacked Nanosheet gate-all-around transistors, a new failure mode between the gate and epitaxial source/drain (PC-Epi) is introduced in the Middle-Of-Line (MOL) intermetal dielectrics (IMD) because of a unique module called inner spacer. In this work, we demonstrate a novel integration scheme for evaluating the inner spacer reliability by completely oxidizing the Si channel. The inner spacer TDDB reliability is also shown to be robust, which is essential to support the continuous aggressive device scaling.

Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet patterning as a replacement to complex double patterning schemes. While front-up sheet pitches and gate pitches expected for the beyond 7nm node fall well within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet variation requirements at technology minimum sheet widths and gate lengths. Here, we explore the crossover point between direct print EUV and optical/EUV based double patterning processes for sheets and gates in the 40 – 50 nm sheet pitch/CPP regime. We demonstrate that to enable the minimum sheet widths of

Horizontally stacked nanosheet gate-all-around devices enable area scaling of transistor technology, while providing improved electrostatic control over FinFETs for a wide range of channel widths within a single chip for simultaneous low power applications and high-performance computing. Fabrication of inner spacers and Si channels is challenging, but essential to device performance, yield, and reliability. We elucidate these challenges and detail their impact to the device. We overcome these challenges with novel, highly selective, isotropic SiGe dry etch techniques which enable precise, robust inner spacer and channel formation. Finally, we demonstrate substantial improvements to relevant device parameters: resistance, drive current, transconductance, threshold voltage, breakdown voltage, bias temperature instability and overall variability.

We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both gate-contact (CB) to source-drain local interconnect (LI) shorts and the LI-contact (CA) to gate shorts is the shape of the LI cap. A trapezoid-shaped oxide (SiO 2 ) LI cap with an appropriate taper angle eliminates shorting between the contacts in the gate and source-drain region. We further demonstrate that this oxide LI cap is fully compatible with Cobalt (Co) metallization with a novel selective tungsten (W) growth process. Additionally, this process enables the SRAM cross-couple (XC) in the same metallization level, eliminating the need for an upper level wiring and greatly simplifying routing in the SRAM cell.

In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.

In this paper, we report the bias temperature instability (BTI) reliability in stacked gate-all-around (GAA) nanosheet (NS) devices. We show that, in addition to its superior intrinsic performance over FinFET and stacked nanowire (NW), stacked NS can also provide NBTI reliability benefit, owing to domination of (100) surface conduction and mitigation of field enhancement effect in ultra-scaled GAA structure.

The characteristics of Stacked Nanosheet are investigated, focusing on channel geometry. For the first time, “narrow sheet effect” on carrier transport is observed. By comparing measured electron $(\mu_{e})$ and hole $(\mu_{h})$ mobilities, and the n-type/p-type opposite transconductance ( $gm$ ) trends versus sheet width ( $Wsheet$ ), we show that the mobility dependency on $Wsheet$ is attributed to reduced (100) plane conduction contribution as $Wsheet$ shrinks.

As device scaling continues, controlling defect densities on the wafer becomes essential for high volume manufacturing (HVM). One type of defect, the non-selective SiGe nodule, becomes more difficult to control during SiGe epitaxy (EPI) growth for p-type field effect transistor (pFET) source and drain. The process window for SiGe EPI growth with low nodule density becomes extremely tight due to the shrinking of contact poly pitch (CPP). Any tiny process shift or incoming structure shift could introduce a high density of nodules, which could affect device performance and yield. The current defect inspection method has a low throughput, so a fast and quantitative characterization technique is preferred for measuring and monitoring this type of defect. Scatterometry is a fast and non-destructive in-line metrology technique. In this work, novel methods were developed to accurately and comprehensively measure the SiGe nodules with scatterometry information. Top-down critical dimension scanning electron microscopy (CD-SEM) images were collected and analyzed on the same location as scatterometry measurement for calibration. Machine learning (ML) algorithms are used to analyze the correlation between the raw spectra and defect density and area fraction. The analysis showed that the defect density and area fractions can be measured separately by correlating intensity variations. In addition to the defect density and area fraction, we also investigate a novel method – model-based scatterometry hybridized with machine learning capabilities – to quantify the average height of the defects along the sidewall of the gate. Hybridizing the machine learning method with the model-based one could also eliminate the possibility of misinterpreting the defect as some structural parameters. Furthermore, cross-sectional TEM and SEM measurement are used to calibrate the model-based scatterometry results. In this work, the correlation between the SiGe nodule defects and the structural parameters of the device is also studied. The preliminary result shows that there is strong correlation between the defect density and spacer thickness. Correlations between the defect density and the structural parameters provides useful information for process engineers to optimize the EPI growth process. With the advances in the scatterometry-based defect measurement metrology, we demonstrate such fast, quantitative, and comprehensive measurement of SiGe nodule defects can be used to improve the throughput and yield.

Multi-channel gate all around (GAA) semiconductor devices require measurements of more target parameters than FinFET devices, due in part to the increased complexity of the different structures needed to fabricate nanosheet devices. In some cases, multiple measurement techniques are required to be used in a hybrid-metrology technique in order to properly extract the necessary information. Optical scatterometry (optical critical dimension, or OCD) is an inline metrology technique which is used to measure the geometrical profile of the structure, but it may not ordinarily be sensitive to very small residues. X-ray based metrologies, such as x-ray fluorescence (XRF) can be used to identify which materials are present in the structure, but are not able to measure profile information for complex 3D structures. This paper reviews a critical etch process step, where neither OCD nor XRF can extract all of the necessary information about the structure on their own, but, when hybridized, are able to provide enough information to solve the application. In GAA structures, the nanosheets are formed from alternating layers of thin SiGe and Si layers which are deposited on a bulk Si substrate. To form the nFET channel, the SiGe must be removed. However, in some cases, there is still remaining SiGe residue on the surface of the Si nanosheets, present in small amounts that are difficult to measure with conventional OCD. Additionally, it is desirable to know at which level of the stacked nanosheets the residue is present. In order to properly characterize the amount of SiGe remaining, data from both OCD and XRF are used. By measuring before and after the etch, the XRF can calculate the percentage of SiGe that is remaining after the etch. This percentage can be used as a constraint in the OCD model to allow the OCD to accurately measure the amount of SiGe, and to enable the OCD model to identify the location of the residue.

In this paper, we report multi-threshold-voltage (multi-Vt) options for stacked Nanosheet gate-all-around (GAA) transistors. V t can be modulated through workfunction metal (WFM) thickness as well as the inter-nanosheet spacing (T sus ), the combination of which may be leveraged to increase the number of undoped V t offerings within a CMOS device menu relative to a FinFET CMOS device menu, which fundamentally does not have T sus as a V t tuning option. Hence we propose our multi-V t scheme by taking advantage of the unique structure of stacked GAA transistor.