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The effect of process-induced defects on the photo-generated charge-carrier lifetime and solar cell performance is critical, which will help optimize the process recipe. In this work, we attempt to quantify the effects of process-induced defects during boron implantation on the n-type silicon wafer in different annealing ambiences. We have evaluated the role of defects that can be formed during oxygen and inert ambience annealing on n-type bifacial passivated emitter rear totally diffused solar cells using a recombination current prefactor (J0). The numerically calculated J0 is calibrated with the reported experimental J0 values using two different methods: (i) Shockley–Read–Hall lifetime and (ii) effective trap-density method. In the latter method, we used the simulated defect density profiles. Both methods capture the process-induced degradation. We observed that the process-induced defects could deteriorate by almost 1% absolute efficiency for the considered annealing conditions. We found that dislocation loops alone cause an ignorable effect on terminal characteristics, but other process-induced mechanisms could dominantly degrade the cell's performance. To further support, we show that independent defects (apart from coupled defects) other than dislocation loops could explain the experimentally reported boron-implanted diodes' J–V curves under reverse bias conditions. [ABSTRACT FROM AUTHOR]

This work presents 3-D mixed-mode simulation results of single event transients (SET) in SiGe HBT emitter followers. The impact of circuit design parameters, including biasing current and resistance are detailed. A simple increase of biasing emitter current is shown to be ineffective for hardening. Instead, during SET, the emitter voltage upset simply follows the base voltage upset due to the inherent nature of the emitter follower topology during circuit operation. The duration and the peak value of the base voltage upset are determined by the impedance and electric field between collector and base. As a result, the use of a smaller base biasing resistance is desirable for reducing SETs in emitter followers. Index Terms--Charge collection, heterojunction bipolar transistors, radiation hardening by design, single event effects, single event transients.

Microbeam measurements and TCAD simulations are used to examine the effects of ion angle of incidence on the charge collected from events occurring in a Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT). The results identify the geometrically driven charge-collection mechanisms that dominate the low LET broad beam SEU response. The deep trench isolation that surrounds the transistor significantly modulates the charge transport and, therefore, the charge collected by the collector. A new way of estimating critical charge, [Q.sub.crit], for upset in SiGe HBT circuits is proposed based on TCAD simulation results and measured broadbeam data. Index Terms--Deep trench isolation (DTI), HBT, IBICC, silicon germanium (SiGe), single event upset (SEU), TCAD.

This paper presents a SEU hardening approach that uses a dummy collector to reduce charge collection in the main transistor. The dummy collector is obtained using the silicon space between adjacent HBTs. It is obtained without any process modification or area penalty. The simulations are performed for normal and angled strikes. The hardened device shows significant reduction in charge collection due to sharing of diffusive charge collection by the dummy collector. Multiple HBT arrays of regular and hardened HBT are simulated to study the simultaneous charge collection in multiple HBTs. With hardening, charge collection in multiple devices is suppressed considerably for normal and angled strikes as the shared dummy collector collects a large amount of charge. Index Terms--Critical charge, deep trench isolation (DTI), dummy collector, radiation hardening by design (RHBD), SiGe HBT, single event upset (SEU), SRH recombination.

Delayed charge collection from ionizing events outside the deep trench can increase the SEU cross section in deep trench isolation technologies. Microbeam test data and device simulations demonstrate how this adverse effect can be mitigated through substrate engineering techniques. The addition of a heavily doped p-type charge-blocking buried layer in the substrate can reduce the delayed charge collection from events that occur outside the deep trench isolation by almost an order of magnitude, implying an approximately comparable reduction in the SEU cross section. Index Terms--Deep trench isolation, Ion Beam Induced Charge Collection (IBICC), silicon germanium, Single Event Upset (SEU), substrate engineering.

This paper presents the three-dimensional simulation of heavy-ion induced charge collection in SiGe heterojunction bipolar transistors (HBTs) on silicon-on-insulator (SOI). Charge collection is found to be independent of the thickness of n+ buried layer, part of the SOI film, which directly relates to the collector resistance. The simulation results show that potential perturbation is confined within a thin region near the collector-base junction, due to the heavy doping of the [n.sup.+] layer. Comparisons with bulk SiGe HBTs show that the charges collected by the collector and substrate are much smaller in SOI than in bulk HBTs, primarily because of the removal of the collector-substrate pn junction. The charges collected by the emitter and base, however, are nearly identical in SOI and bulk HBTs, because the heavily doped [n.sup.+] buried layer decouples the potential perturbation and hence charge collection in the intrinsic emitter, base and collector from those in the collector-substrate junction. The load dependence of charge collection is also examined. Index Terms--Heterojunction bipolar transistors (HBTs), silicon-on-insulator (SOI).

This paper presents the first 3-D simulation of heavy-ion induced charge collection in a SiGe HBT, together with microbeam testing data. The charge collected by the terminals is a strong function of the ion striking position. The sensitive area of charge collection for each terminal is identified based on analysis of the device structure and simulation results. For a normal strike between the deep trench edges, most of the electrons and holes are collected by the collector and substrate terminals, respectively. For an ion strike between the shallow trench edges surrounding the emitter, the base collects appreciable amount of charge. Emitter collects negligible amount of charge. Good agreement is achieved between the experimental and simulated data. Problems encountered with mesh generation and charge collection simulation are also discussed. Index Terms--Deep trench, DESSIS, HBT, LET, mesh, polysilicon emitter, shallow trench, SIMS, SRIM, UHV/CVD.

Agrivoltaics (AV) allows double usage of the land by yielding both food and energy. Such farms are more suitable for high population density locations like India. In this work, we study the impact of the vertical, bifacial AV farm on the rice (Oryza sativa) yield in a hot, tropical climate prevailing in the south-eastern part of India (Chennai, 13.0827° N, 80.2707° E). We compare two different bifacial silicon solar cell technologies: (a) passivated emitter rear contact (PERC+), and (b) silicon heterojunction (SHJ), using vertical configurations. We show that SHJ yields more energy than PERC for the considered location, mainly due to its high-temperature coefficient, high inherent bifaciality, spectral and the temperature advantage of the vertical configuration. To maximize both the rice and energy yield with equal importance, we discuss two strategies: (a) varying the pitch of the panels (2 m and 4 m) (b) optimizing the spectral sharing between the panels and plants by reflecting the photosynthetically active radiation incident over the panels (2 m pitch). We found that increasing the pitch of the panels (4 m pitch) could improve the rice yield but drastically reduces the energy yield (∼45% compared to an optimal photovoltaics (PV) farm). Using simulation, we show that by reflecting the small portion of the spectrum (400–500 nm) incident on the PV panels (an additional advantage of the vertical configuration), both the rice and energy yield could achieve a win–win situation (∼80% of rice yield compared to an open farm and 74% of the energy yield compared to an optimally tilted PV farm) with a higher land equivalent ratio of 1.54. The disadvantage of SHJs in the PV farm becomes advantageous in an AV farm due to its low dependence on the reflected portion of the spectrum compared to PERC+ solar cells. This work will motivate the development of low-cost technologies to make spectral sharing a viable option in the future, considering the limited availability of the land. [ABSTRACT FROM AUTHOR]

This work presents 3-D mixed-mode simulation results of single event transients (SET) in SiGe HBT emitter followers. The impact of circuit design parameters, including biasing current and resistance are detailed. A simple increase of biasing emitter current is shown to be ineffective for hardening. Instead, during SET, the emitter voltage upset simply follows the base voltage upset due to the inherent nature of the emitter follower topology during circuit operation. The duration and the peak value of the base voltage upset are determined by the impedance and electric field between collector and base. As a result, the use of a smaller base biasing resistance is desirable for reducing SETs in emitter followers. [ABSTRACT FROM PUBLISHER]