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Contactless plating with electroless solutions can provide self-aligned high-efficiency contacts with very low silver content, using simple and inexpensive equipment. With prior surface activation, it can even be used to metallize both sides of bifacial silicon solar cells simultaneously. However, we observe in such a coplating process with nickel, where surface activation is achieved by immersion plating and thickening by electroless plating, that V oc and fill factor can sometimes significantly decrease with immersion-plating time. To understand the reason for this electrical degradation, we studied the impact of immersion plating on the microstructure of the plated silicon surface. The evolution of the Si-Ni interface was studied by scanning and transmission electron microscopies, energy-dispersive X-ray analysis, secondary ion mass spectrometry, and scanning spreading resistance microscopy. Our attention focused on metal in-diffusion, silicon roughening and etching as the origin for increased recombination. Etching was found to have a significant impact on V oc. The thickness of N + Si etched during Ni deposition can in fact suppress in a few locations most of the field-effect passivation underneath the contacts. This means that a thicker surface field with doping beyond 1019/cm3 must be foreseen under the plated areas, or that the amount of Si lost in the reaction must be reduced. Our observations also confirm that immersion plating can hinder silicide formation and allow Ni in-diffusion, which may be a concern for reliability.

Perovskite/crystalline-silicon (c-Si) tandem solar cells offer a viable roadmap for reaching power conversion efficiencies beyond 30%. In this configuration, however, the silicon cell now mainly receives an infrared rich illumination spectrum where the absorption coefficient of silicon is poor. To boost the light absorption in this wavelength interval, transmitted through the top cell, a solution is to introduce a dedicated nanoscale texture on the front side of the silicon bottom cell and tweaking the optical elements in its design. These optical elements are manifold, with tunable geometrical dimensions, layer thicknesses, and refractive indices. For optically optimizing nanostructured silicon solar cells, electromagnetic wave solving methods, such as the rigorous coupled-wave analysis (RCWA), are normally used but they become computationally infeasible when several design variables are involved in an optimization problem. In this work, a natural selection algorithm, known as the genetic algorithm, is coupled with RCWA for extracting the optimal values of various design parameters in four-terminal perovskite/c-Si tandem devices in parallel. Both two-side-contacted and interdigitated back-contacted silicon heterojunction cell structures, featuring an inverse nanopyramid grating texture on the front, are optimized for five interdependent variables using a genetic algorithm for the bottom cell application and benchmarked against their random pyramid textured analogs. Our study shows that an optimized inverse nanopyramid grating texture can outperform the standard random pyramid texture when considering incidence angle variations. More importantly, the study illustrates how a genetic algorithm can support modeling complex solar cell structures with numerous degrees of freedom.

Carefully tailored periodic nanostructures on the light wavelength scale, such as diffraction gratings, benefit from wave optics for efficiently trapping the weakly absorbing infrared photons in crystalline-silicon (c-Si) absorbers. In contrast with the conventional random pyramid texture, diffraction gratings can be designed to target specific wavelength ranges by the selection of the grating pitch. Absorption enhancement at infrared wavelengths in a silicon solar cell is especially desired when it operates below a perovskite top cell in a tandem device. In this article, inverse nanopyramid gratings of 800 nm pitch are proposed as an alternative front-surface texture to random pyramids in silicon heterojunction devices with interdigitated back contacts that are to be used as bottom cells in four-terminal perovskite/c-Si tandem devices. By doing so, we report a short-circuit current density gain of 0.53 mA/cm 2 with respect to the random pyramid texturing for the bottom c-Si cell. The rationale to substitute random pyramids by inverse nanopyramid gratings is, however, not justified in single-junction operation despite achieving the power conversion efficiency of 22.3% since the degraded optical performance at shorter wavelengths offsets the absorption enhancement at longer wavelengths, resulting in similar levels of short-circuit current densities for both texture types. ispartof: Ieee Journal Of Photovoltaics vol:10 issue:3 pages:740-748 status: Published online

The Umicore Ge-on-Ge engineered substrate concept consists of a thin epi-ready germanium foil that is weakly attached to a bulk germanium mother substrate. The weak layer is made through modification of the front side of the bulk substrate and allows for easy detachment at any point in the solar cell manufacturing flow. The mother substrate is intended to be re-used multiple times. This paper will present the growth and characterization of III-V layers on Ge-on-Ge engineered substrates as well as the subsequent GaInP single junction device fabrication and characterization. The Voc of the solar cells was unaffected, which proved the similar performance of bulk Ge and engineered Ge-on-Ge as epi-templates.

Specific power is an important metric for solar arrays in the aerospace market. For High Altitude Pseudo Satellites (HAPS), solar cells specific powers above 1500 W/kg are targeted. The current standard technology for space applications, namely lattice matched triple junction solar cells grown on $145\ \mu\mathrm{m}$ thick germanium substrates, supplies the required efficiency but is not light enough. This paper will present the Ge-on-Ge engineered substrate concept as an approach that can be implemented to address the needed reduction in germanium substrate thickness. The lift-off of the top Ge foil from this Ge-on-Ge substrate will be demonstrated. Additionally, results of epitaxial growth of III-V layers onto Ge-on-Ge engineered substrates will be discussed.

One of the advantages of an epitaxially grown emitter is that its doping profile is not limited by the diffusion process and that almost any arbitrary profile shape can be realized. In this simulation study we make use of the epitaxial doping profile’s flexibility to optimize the emitter of an nPERT solar cell. Initially an optical and electrical model is set up in Sentaurus TCAD and calibrated based on measurements of an actual device with an efficiency of 22.5%. Next, simulations for a box shaped profile with varying thicknesses and doping concentrations are carried out. Additionally, a two-step emitter consisting of a combination of two box profiles – one located at the surface and another deep profile underneath the former one – is also simulated. The results clearly identify the optimal doping concentrations and thicknesses which result in the highest efficiencies. Outside of these optimal regions the most significant loss mechanisms are pointed out. To be highlighted is that the switch from a the single box profile emitter to an optimal two-step profile emitter realizes a gain of 0.4% absolute resulting in an efficiency of 22.9%. This demonstrates that the freedom in the shape of the epitaxial doping profile can be employed to further increase the solar cell efficiencies.

Previously, IMEC proposed the i(2)-module concept which allows to process silicon heterojunction interdigitated back-contact (SHJ-IBC) cells on thin ( < 50 mu m) Si wafers at module level. This concept includes the bonding of the thin wafer early on to the module cover glass, which delivers mechanical support to the wafer and thus significantly improves the production yield. In this work, we test silicone and ethylene vinyl acetate bonding agents and prove them to be resistant to all rear side processes, including wet and plasma processes. Moreover, a lift-off process using a sacrificial SiOx layer has been developed for emitter patterning to replace conventional lithography. The optimized process steps are demonstrated by the fabrication of SHJ-IBC cells on 6-inch 190 mu m-thick wafers. Efficiencies up to 22.6% have been achieved on reference freestanding wafers. Excellent V-oc of 734 my and J(sc) of 40.8 mA/cm(2) lead to an efficiency of 21.7% on silicone-bonded cells, where the high V-oc indicates the process compatibility of the bonding agent. The developments that enabled such achievements and the key factors that limit the device performance are discussed in this paper. The authors would like to thank the financial support of imec's industrial affiliation program for Si-PV. This work was also partially funded by Kuwait Foundation for the Advancement of Sciences under project code: P115-15EE-01. The research has received funding from the European Union's Seventh Programme for research, technological development and demonstration under grant agreements no. 609788 (Cheetah), and also funding from the European Union's Horizon 2020 research and innovation programme under the Marie Sklodowska-Curie grant agreement No 657270. The authors gratefully acknowledge Joachim John for the spectral response measurements and Yiming Yang for the SEM measurements.

International audience; Thin film solar cells may exhibit high conversion efficiencies provided their active material exhibits a high quality, like in the case of crystalline silicon, and if incident light coupling and absorption are appropriately controlled. We propose to integrate an advanced light trapping process relying on photonic crystals including a controlled pseudo-disorder. Thanks to Rigorous Coupled Wave Analysis, we determine the optimized nanophotonic structures that should be appropriately introduced in 1 µm thick crystalline silicon layers standing on a metal layer like aluminum. Thanks to a carefully controlled pseudo-disorder perturbation, absorption in these designed nanopatterns overcome that predicted in the case of fully optimized square lattice photonic crystals. Fabricated structures are analyzed in light of this numerical investigation to evidence the impact of such controlled perturbations, but also the influence of the measurement method and the technological imperfections. Thanks to the optimized perturbated photonic crystals, the integrated absorption in 1 µm thick crystalline Silicon layer increases from 37.7%, in the case of the unpatterned stack, to 70.7%. The sole effect of pseudo-disorder on the fully optimized simply periodic photonic crystals leads to an absolute increase of the integrated absorption up to 2%, as predicted by simulations, while both structures are fabricated using exactly the same process flow.

Utilisation of expensive silicon (Si) material in crystalline Si modules has come down to 4 g Si per watt-peak in 2018, mainly as a result of reduction in wafer thickness and kerf losses as well as increase in module efficiencies. With continued progress in conventional multi-wire sawing of ingots, wafers as thin as 100 mu m could eventually be produced. Beyond this, kerfless lift-off technologies are being investigated which enable wafer thicknesses well below 100 mu m with negligible Si kerf waste. Such thin Si wafers and foils would be much lighter in weight than today's standard 165-180 mu m-thick wafers and would exhibit considerable flexibility and fragility. This necessitates a rethink about how to handle and process thin Si into solar devices in a manufacturing line with high mechanical yield and high throughput. This paper gives a broad overview of the different approaches for fabricating solar cells on thin Si foils. In particular, three routes are discussed in detail, namely (1) freestanding processing of thin Si, (2) processing of thin Si supported mechanically on a conductive low-cost Si substrate ("wafer-equivalent" approach) and (3) processing of thin Si bonded to a transparent glass superstrate. In each case, the main challenges are explained and the recent progress in addressing them are summarised. Kerfless 50 mu m-thick epitaxial Si foils lifted-off using porous Si and thinned-down Si wafers (below 70 mu m) are used as model substrates for this work. The authors gratefully acknowledge the efforts of several people who were involved in this work over the last few years, namely Jonathan Govaerts, Stefano Granata, Menglei Xu, Ergi Donercark, Ivan Sharlandshiev, Shashi Kiran Jonnak, Shruti Jambaldinni, Robert Roozeman, Jarkko Heildcinen, Thomas Kaden, Zuzana Kovacova, Erich Neubauer, Michael Grimm and Kaori Nagaoka. The authors also acknowledge the funding received for this work from the European Commission for the H2020 project CABRISS under grant agreement No. 641972. Imec is a partner in EnergyVille (www.energyville.be), a collaboration between the Flemish research partners KU Leuven, VITO, imec, and UHasselt in the field of sustainable energy and intelligent energy systems. Radhakrishnan, HS (reprint author), Imec Vzw Partner EnergyVille, Kapeldreef 75, B-3001 Leuven, Belgium. sivarama@imec.be

Owing to its compatibility with mainstream Si technologies and remarkable physical properties, Ge has become a key enabler of modern semiconductor devices. In the past decades, the element has been introduced in various application areas such as high-performance and high-speed electronics, integrated photonics, photovoltaics, sensors and spintronics [1-2]. Its alloying with Si has for instance benefited the performance and power consumption of bipolar and CMOS transistors thanks to an increase in source/drain active doping concentration and channel carrier mobility. In its pure form, Ge has drawn a lot of attention for the integration of Ge nMOS devices [3-4], near-to-mid-infrared photodetectors and modulators [5-6] and as a substrate for multijunction solar cells [7], for which carrier mobility and lifetime are critical parameters. The fabrication of high-quality, scalable, relatively thin although fully relaxed Ge/Si virtual substrates (VS) is of utmost importance to enable and integrate these technologies at reduced costs. The monolithic epitaxial growth of Ge on Si however suffers from intrinsic limitations, due to the large lattice mismatch between the two materials inevitably causing the formation of a high-density network of misfit dislocations at the Ge/Si heterointerface. The inherent presence of large quantities of non-radiative recombination centers in this region has so far restricted the industrial use of Ge VS. Keeping the charge carriers away from the interface could nevertheless be in most cases an appropriate solution to contain their detrimental impact [8]. Growing thick Ge layers is a way to achieve this goal and reduce the material defectivity [9]. Unfortunately, quality improvements are limited and thicknesses exceeding 5 µm required to enter the sub 1E6 cm-2 threading dislocation density (TDD) range. This makes the process very time-consuming, expensive and induces a severe wafer bow. Another possibility consists in suppressing the defective part of the material. This can be done by splitting the Ge VS to isolate the top part of the layer from the Ge/Si interface. This method allows for performance improvements in case the replacement interface does not incur a greater penalty. In this contribution, we therefore evaluate the properties of Ge-on-nothing (GeON) suspended foils and benchmark extracted carrier lifetimes against those measured in blanket Ge/Si with different thicknesses. The concept, initially introduced by Sato et al. [10] and developed by imec to form silicon-on-nothing [11], is here applied to Ge VS, as presented in [12]. The process results in a ~ 1.2-1.4 µm thick Ge foil separated from the substrate (Figure 1) and is compared with blanket Ge VS with thicknesses ranging from 0.2 to 4.9 µm. Electron channeling contrast imaging (ECCI) and time-resolved photoluminescence (TR-PL) spectroscopy at the Ge direct bandgap are used to estimate the threading dislocation density and the free-carrier lifetime in the samples, respectively. Figure 2 and Table 1 summarize the results of this study. As expected, the estimated TDD decreases with increasing the Ge layer thickness. A minimum TDD value of ~ 4E6 cm-2 is obtained with the thicker Ge film (~ 4.9 µm thick, sample F). The GeON sample (sample D), does not stand out of the trend. On the other hand, the carrier lifetime obtained in sample D (> 30 ns) clearly outperforms those obtained for the different Ge VS (< 15 ns). This indicates that the recombination velocity at the newly formed Ge bottom surface is much lower than the one initially introduced by the defective Ge/Si interfacial region. Containing the carriers closer to this area by decreasing the thickness of the Ge VS strongly degrades their lifetime and compromises the material optical properties. We infer that GeON foils have an interesting potential for applications necessitating maximal lifetimes. References: [1] M. Bosi and G. Attolini, Progress in Crystal Growth and Characterization of Materials, 56(3-4), 146 (2010); [2] D. Paul, Semiconductor Science and Technology, 19 R75 (2004); [3] M. J. H. van Dal et al., IEEE International Electron Devices Meeting, 492 (2018); [4] H. Arimura et al., IEEE Transactions on Electron Devices, 66(12), 5387 (2019); [5] D. Marris-Morini et al., Nanophotonics, 7(11), 1781 (2018); [6] H. Chen et al., Journal of Lightwave Technology, 35(4), 722 (2017); [7] H. Cotal et al., Energy Environ. Sci., 2, 174 (2009); [8] R. Geiger et al., Applied Physics Letters, 104, 062106 (2014); [9] G. Wang et al., Applied Physics Letters, 94(10), 102115 (2009); [10] T. Sato et al., Symposium on VLSI Technology Digest Technical Papers, 206 (1998); [11] V. Depauw et al., Thin Solid Films, 516(20), 6934 (2008); [12] R. Loo et al., ECS Transactions, 98(5), 195 (2020). Figure 1

International audience; The homoepitaxy of Si is particularly interesting for the purpose of kerfless wafer production, for example in the photovoltaic domain. Substrate surface engineering is a key step prior to epitaxial growth, which will affect the quality of the epitaxial layer and its detachment for layer transfer. In this work, we propose two plasma-based surface engineering methods including the deposition of a bilayer homoepitaxial interface and a SiGe heteroepitaxial interface. Their impact on the crystalline quality of epitaxial Si layers grown both by plasma enhanced chemical vapor deposition (PECVD) at 200 °C and by atmospheric pressure chemical vapor deposition (APCVD) at 1130 °C are explored. Stacking faults are observed in epitaxial Si layers with an ultra-thin epitaxial Si interface layer. For surface engineering method based on the 2 addition of an interfacial heteroepitaxial SiGe layer, higher interfacial hydrogen content and better bulk epitaxial Si quality are observed in comparison with interfacial homoepitaxial Si layer.

Developing new materials with improved thermal stability is very important as far as the passivation and processing of crystalline silicon solar cells is considered. In this work, we studied two types of hydrogenated silicon based materials (hydrogenated amorphous silicon oxide and hydrogenated microcrystalline silicon oxide) and compared them to the well-established hydrogenated amorphous silicon. We demonstrate the thermal robustness of hydrogenated silicon oxide under anodic bonding conditions (250 °C, 1000 V). The microstructural and composition evolution of passivation layers under anodic bonding was characterized by Fourier transform infrared spectroscopy, high resolution transmission electron microscopy, annular dark-field scanning transmission electron microscopy, energy-dispersive X-ray spectroscopy and secondary ion mass spectrometry. We found that oxygen can inhibit the degradation of the passivation quality under anodic bonding by suppressing the localized interfacial crystallization and re-passivating the interface. When applied to thin-film crystalline silicon solar cells, the excellent thermal robustness of hydrogenated microcrystalline silicon oxide allows to keep a good passivation to the ultrathin c-Si absorbers (1 μm).

In order to reduce the material cost for silicon solar cells, several research groups are investigating methods to minimize the silicon consumption for making monocrystalline silicon wafers. One promising approach is deposition of an epitaxial layer on porous silicon, followed by detachment of the layer. This contribution discusses improvements in the epitaxial wafer fabrication by optimization of the porosification process. The introduction of a layered porous silicon structure allows to independently improve both epitaxial layer quality and detachment yield. In this way, we have managed to obtain 100µm thick silicon wafers with effective lifetimes up to 1.3ms, and 40µm thick wafers with effective lifetimes up to 700µs. We will also review the current status of the process development for solar cells made on thin wafers. Two approaches are presented. In the first approach, heterojunction solar cells are fabricated on freestanding epitaxial wafers of 40µm thickness. In the second approach, high efficiency (21%) heterojunction back-contacted cells are fabricated on wafers that are bonded to a glass superstrate. Challenges for device processing and limitations in cell performance are discussed.

Fabrication of high-quality ultrathin monocrystalline silicon layers and their transfer to low-cost substrates are key steps for flexible electronics and photovoltaics. In this work, we demonstrate a low-temperature and low-cost process for ultrathin silicon solar cells. By using standard plasma-enhanced chemical vapor deposition (PECVD), we grow high-quality epitaxial silicon layers (epi-PECVD) from SiH4/H2 gas mixtures at 175 °C. Using secondary ion mass spectrometry and transmission electron microscopy, we show that the porosity of the epi-PECVD/crystalline silicon interface can be tuned by controlling the hydrogen accumulation there. Moreover, we demonstrate that 13–14% porosity is a threshold above which the interface becomes fragile and can easily be cleaved. Taking advantage of the H-rich interface fragility, we demonstrate the transfer of large areas (∽10 cm2) ultrathin epi-PECVD layers (0.5–5.5 µm) onto glass substrates by anodic bonding and moderate annealing (275–350 °C). The structural properties of transferred layers are assessed, and the first PECVD epitaxial silicon solar cells transferred on glass are characterized. Copyright © 2016 John Wiley & Sons, Ltd.

Future monolithic heterogeneous integration of Ge and IIIV materials in electronic, optoelectronic and photonic devices requires advanced layer transfer and 3D device stacking technologies, which starts with the fabrication of suitable (virtual) substrates. A layer transfer process based on the reorganization of macro-porous Si at high temperature was developed by imec [1]. The developed fabrication scheme to fabricate macropores is based on standard UV lithography and dry etching techniques rather than electrochemical etching. This enables an easy transfer to full Si wafers (up to 300 mm). During a high-temperature step, the top part of the macro-porous Si reflows. By using proper anneal conditions, the layer detaches from the mother substrate, being anchored by a few attachment points only, forming a ‘Si on nothing’ (SoN) stack (Fig. 1a). The suspended Si layer can then easily be transferred to another substrate. In this contribution, we assess the suitability of macro-porous Si and SoN as starting material for Ge virtual substrates. The goal is to provide a fabrication scheme that allows an easy detachment of the virtual substrate after wafer to wafer bonding. Macro-porous Si was only fabricated in the inner 10x10 cm2 area of 200 mm wafers using imec’s qualified fabrication scheme. Ge layers were simultaneously grown on the inner macro-porous Si (or SoN) and the outer bulk Si. This allows to compare the material properties without the risk of wafer to wafer variations due to non-reproducibility issues. Our approach for making macro-porous Si and SoN provides mono-crystalline, nearly defect-free, and extremely smooth Si starting surfaces. A standard low temperature epitaxial Ge growth process in an ASM-Epsilon® 2000 system was used to deposit the Ge layers [2]. As an example, Fig. 1b shows a 1.25 mm thick mono-crystalline epitaxial Ge layer grown on a macro-porous Si layer. The Ge growth proceeds in a 2-dimensional mono-crystalline growth mode. The surface morphology of the grown Ge is not affected by the starting surface (Fig. 1c,d). The Full Width at Half Maximum (FWHM) as extracted from w-2q High Resolution X-ray Diffraction scans acquired around the Ge (004) Bragg peak is strongly reduced after a post Ge deposition anneal, which was also reported for Ge on bulk Si [2]. Threading dislocations annihilate during the post-epi anneal. FWHM values as low as 160 arc sec have been measured for 1.25 mm thick Ge layers independent of the underlying layer. This reflects the high material quality of the grown Ge. The difference in thermal expansion coefficient between Si and Ge results in some tensile stress in the annealed Ge layer, which explains the well-known shift in XRD peak position. The improvement in material quality by using a post-epi anneal is also reflected in the carrier lifetime as extracted from room-temperature photoluminescence measurements. The carrier lifetime increases from -2) and close to the values expected from literature. The material properties listed above are not affected by the thickness of the closed Si layer in-between the Ge and the porous Si. In conclusion, we developed a fabrication scheme for strain-relaxed Ge grown on SoN (or on macroporous Si) starting from conventional Si substrates. The material properties of the virtual Ge substrate are identical to those obtained for Ge grown on bulk Si. The virtual substrate serves as starting material for layer transfer and 3D device stacking technologies. The fabrication scheme can be extended to (defect free) bulk Ge for which the fabrication of Ge on nothing followed by layer transfer has been demonstrated [3]. References: [1] V. Depauw et al., Thin Solid Films 516, 6934 (2008) [2] P. Fakhimi et al. 10th Int. Conf. on Silicon Epitaxy and heterostructures (ICSI), book of abstracts, p. 191 (2017) [3] S. Park et al., Joule 3 (7), 1782 (2019) Figure 1

Dry plasma etching, commonly used by the Photonics community as the etching technique for the fabrication of photonic nanostructures, could be a source of device performance limitations when used in the frame of silicon photovoltaics. So far, the lack of silicon solar cells with state-of-the-art efficiencies utilizing nanophotonic concepts shows how challenging their integration is, owing to the trade-off between optical and electrical properties. In this study we show that dry plasma etching results in the degradation of the silicon material quality due to (i) a high density of dangling bonds and (ii) the presence of sub-surface defects, resulting in high surface recombination velocities and low minority carrier lifetimes. On the contrary, wet chemical anisotropic etching used as an alternative, leads to the formation of inverted nanopyramids that result in low surface recombination velocity and low density of dangling bonds. The proposed inverted nanopyramids could enable high efficiency photonic assisted solar cells by offering the potential to achieve higher short-circuit current without degrading the open circuit voltage. (© 2016 WILEY-VCH Verlag GmbH &Co. KGaA, Weinheim)

In the frame of the development of thin crystalline silicon solar cell technologies, surface nanopatterning of silicon is gaining importance. Its impact on the material quality is, however, not yet fully controlled.We investigate here the influence of surface nanotexturing on the series resistance of a contacting scheme relevant for thin-film crystalline silicon heterojunction solar cells. Two dimensional periodic nanotextures are fabricated using a combination of nanoimprint lithography and either dry or wet etching, while random pyramid texturing is used for benchmarking. We compare these texturing techniques in terms of their effect on the series resistance of a solar cell through a study of the sheet resistance (Rsh ) and contact resistance (Rc) of its front layers, i.e., a sputtered transparent conductive oxide and evaporated metal contacts. We have found by four-point probe and the transfer length methods that dry-etched nanopatterns render the highest Rsh and Rc values. Wet-etched nanopatterns, on the other hand, have less impact on Rc and render Rsh similar to that obtained from the nontextured case., Authors' post-print version in Abdo et al., IEEE Journal of Photovoltaics, July 2015

Two important aspects for the success of the porous silicon-based layer transfer method in producing kerfless thin ( 15 cm −3 which corresponds to a minimum minority carrier diffusion length of ~670 µm (> 16 times the silicon thickness). With such high quality epitaxial foils combined with high detachment yield, very high efficiency solar devices on thin silicon substrates would be a reality in the near future.

We have studied surface passivation on nanopatterned crystalline silicon (c-Si) wafers (280 µm), thin c-Si wafers (25 µm), ultrathin (~1–6 µm) low temperature epitaxial PECVD and epitaxy-free silicon. Nanopatterned front surfaces were produced by combining nanoimprint lithography with dry or wet etching. The impact of the nanopatterning on the effective lifetime is investigated by means of photoconductance and time-resolved microwave conductivity measurements. Passivation of flat ultra-thin monocrystalline layers by a-Si:H demonstrates effective lifetimes of a few µs. Flat, dry and wet etched c-Si wafers were also passivated by hydrogenated amorphous silicon, thus forming a heterojunction interface. The measured effective lifetimes were 2.2 ms for the flat, 484 μs for the dry and 709 μs for the wet etched wafers, respectively. It is noteworthy that despite the plasma damage associated with the dry etching process, the lifetime measured after passivation remains high enough for the targeted ultrathin solar cells. Solar cells fabricated on wafers nanopatterned via wet etching have reached an open circuit voltage as high as the flat sample thus demonstrating the potential of the use of wet etched nanopatterned surfaces for high efficiency solar cells.

Texturing of crystalline silicon at the light wavelength scale is a promising approach for light management in ever thinner cells. However, this approach requires adapting the device design and process, which has so far revealed to be a challenging task. Indeed, successful integration requires compromising the excellent optical properties for preserving the electrical ones. We briefly summarize what has been learned so far in the community and illustrate some of these learnings with the fabrication and improvement of 1-μ m-thin monocrystalline nanotextured silicon solar cells.

We propose a back reflecting scheme in order to enhance the maximum achievable current in one micron thick crystalline silicon solar cells. We perform 3D numerical investigations of the scattering properties of metallic nanostructures located at the back side and optimize them for enhancing absorption in the silicon layer. We validate our numerical results experimentally and also compare the absorption enhancement in the solar cell structure, both with quasi-periodic and random metallic nanostructures. We have looked at the interplay between the metallic nanostructures and an integrated back reflector. We show that the combination of metallic nanoparticles and a metallic reflector results in significant parasitic absorption. We compared this to another implementation based on titanium dioxide nanoparticles, which act as a Lambertian reflector of light. Our simulation and experimental results show that this proposed configuration results in reduced absorption losses and in broadband enhancement of absorption for ultra-thin solar cells, paving the way to an optimal back reflector for thin film photovoltaics.

We report on the fabrication, integration, and simulation, both optical and optoelectrical, of two-dimensional photonic nanostructures for advanced light trapping in thin crystalline silicon (c-Si) solar cells. The photonic nanostructures are fabricated by the combination of various lithography (nanoimprint, laser interference, and hole mask colloidal) and etching (dry plasma and wet chemical) techniques. The nanopatterning possibilities thus range from periodic to random corrugations and from inverted nanopyramids to high aspect ratio profiles. Optically, the nanopatterning results in better performance than the standard pyramid texturing, showing a more robust behavior with respect to light incidence angle. Electrically, wet etching results in higher minority carrier lifetimes compared to dry etching. From the integration of the photonic nanostructures into a micron-thin c-Si solar cell certain factors limiting the efficiencies are identified. More precisely: (a) the parasitic absorption is limiting the short circuit current, (b) the conformality of thin-film coatings on the nanopatterned surface is limiting the fill factor, and (c) the material damage from dry etching is limiting the open circuit voltage. From optical simulations, the optimal pattern parameters are identified. From optoelectrical simulations, cell design considerations are discussed, suggesting to position the junction on the opposite side of the nanopattern.

A porous silicon-based layer transfer process to produce thin (30-50 μm) kerfless epitaxial foils (epifoils) is a promising approach toward high-efficiency solar cells. For high efficiencies, the epifoil must have high minority carrier lifetimes. The epifoil quality depends on the properties of the porous layer since it is the template for epitaxy. It is shown that by reducing the thickness of this layer and/or its porosity in the near-surface region, the near-surface void size is reduced to

To push silicon solar cells up to their theoretical limit and, in the meantime, minimize the amount of active material employed, many researchers have proposed to fabricate silicon solar cells starting from substrates of 100 μm or below. A considerable number of methods have been proposed to overcome the limitations of the standard sawing technique but, all of them present some drawbacks. One of these methods, the Slim-cut method, exploits the stress-induced by the deposition of a layer on top of a thick silicon substrate to separate a thin silicon foil. This process however did not solve the issues linked to the processing of free-standing foils. In this work we present a flow to process the Slim-cut foils into solar cells by minimizing the number of process steps performed on free-standing foils to just one step. The possibility to tune the thickness of the obtained silicon foil is investigated both by analytical calculations and experimental results. Moreover, a solution to remove the stress-inducing layer compatible with the flow is reported and lifetime measurements of samples bonded on glass demonstrate that the quality of the samples is high enough for the fabrication of solar cells.

This paper discusses on-going efforts towards reliable lifetime measurements on epilayers and the subsequent decoupling of the bulk and surface recombination components, both while it is still attached to the p+ substrate on which it is grown (“attached epilayer”) and after its detachment from the substrate (“detached epifoil”). For the “attached epilayers”, microwave photoconductance decay (^-PCD) and simulation-assisted photoluminescence (sim-PL) were applied together with a variation in the epilayer thickness to evaluate the bulk lifetime (Tbulk) and total effective surface recombination velocity (Stot) of p-type epilayers. By applying linear fits to reciprocal effective lifetime versus reciprocal epilayer thickness data, Stot of all samples were reliably extracted, resulting in Stot of ∼265 cm/s in the absence of porous silicon at the epilayer/substrate interface compared to ∼9220 cm/s when present and ∼775 cm/s when shielded by a thin back surface field. Based on these Stot values, sim-PL was used to estimate Tbulk to be ∼160 |us in the porous silicon area. For the n-type “detached epifoils”, quasi-steady state photoconductance (QSSPC) was used. However, reliable Tbulk could not be extracted, despite the lower Stot because Tbulk was too high. However, a lower limit to Tbulk was estimated to be >138 μs. Such high bulk lifetimes imply bulk diffusion lengths that are an order of magnitude longer than the epilayer thicknesses, potentially leading to high cell efficiencies.

In the last decades many techniques have been proposed to manufacture thin (Several parameters can be adjusted to change the morphology and, hence, the properties of the porous layer, both in the porous silicon formation and the succeeding thermal treatment. This work focuses on the effect of the parameters that control the porous silicon formation on the structure of the porous silicon layer after annealing and, more specifically, on the roughness of the top surface. The reported analysis shows how the roughness of the seed layer can be reduced to improve the quality of the epitaxial growth.

Module-level processing of silicon heterojunction interdigitated back-contacted (SHJ-IBC) solar cells while bonded to glass, in the so-called i2-module concept, is discussed. In this approach, a key challenge is the interdigitated patterning of a-Si:H without compromising on the rear-surface passivation. Process adaptations involving more resistant bonding agents and a milder wet etchant enabled bonded cells with the best efficiency of 21.7% and Voc of 734 mV, which are the highest reported for bonded cells processed partially at module level, and which undoubtedly proves the potential of this i2-module concept to reach high Voc and efficiency. Yet another challenge is to make the process flow cost-effective and industrially-relevant, i.e. a litho-free, all-dry process flow, analogous to thin-film PV module fabrication. As a first step, dry etching of a-Si:H was developed to replace wet etching, and was successfully incorporated in a SHJ-IBC process flow to fabricate freestanding cells with the best efficiency of 22.9% and above 20% on thick (190 μm) and thin (56 μm) EVA-bonded silicon.

While the number of techniques for patterning materials at the nanoscale exponentially increases, only a handful of methods approach the conformal patterning of strongly non-planar surfaces. Here, using the direct surface self-assembly of colloids by electrostatics, we produce highly conformal bottom-up nanopatterns with a short-range order. We illustrate the potential of this approach by devising functional nanopatterns on highly non-planar substrates such as pyramid-textured silicon substrates and inherently rough polycrystalline films. We further produce functionalized polycrystalline thin-film silicon solar cells with enhanced optical performance. The perspective presented here to pattern essentially any surface at the nanoscale, in particular surfaces with high inherent roughness or with microscale features, opens new possibilities in a wide range of advanced technologies from affordable photovoltaics and optoelectronics to cellular engineering.

The enhancement of light absorption via nanopatterning in crystalline silicon solar cells is becoming extremely important with the decrease of wafer thickness for the further reduction of solar cell fabrication cost. In order to study the influence of nanopatterning on crystalline silicon thin-film solar cells, we applied two lithography techniques (laser interference lithography and nanoimprint lithography) combined with two etching techniques (dry and wet) to epitaxial crystalline silicon thin films deposited via plasma-enhanced chemical vapor deposition at 175 degrees C. The influence of nanopatterning with different etching profiles on solar cell performance is studied. We found that the etching profiles (pitch, depth and diameter) have a stronger impact on the passivation quality (open circuit voltage and fill factor) than on the optical performance (short circuit current density) of the solar cells. We also show that nanopatterns obtained via wet-etching can improve solar cell performance; and in contrast, dry-etching leads to poor passivation related to the etching profile, surface damage, and/ or contamination introduced during the etching process.

We report on the fabrication of disordered nanostructures by combining colloidal lithography and silicon etching. We show good control of the short-range ordered colloidal pattern for a wide range of bead sizes from 170 to 850 nm. The inter-particle spacing follows a Gaussian distribution with the average distance between two neighboring beads (center to center) being approximately twice their diameter, thus enabling the nanopatterning with dimensions relevant to the light wavelength scale. The disordered nanostructures result in a lower integrated reflectance (8.1%) than state-of-the-art random pyramid texturing (11.7%) when fabricated on 700 µm thick wafers. When integrated in a 1.1 µm thin crystalline silicon slab, the absorption is enhanced from 24.0% up to 64.3%. The broadening of resonant modes present for the disordered nanopattern offers a more broadband light confinement compared to a periodic nanopattern. Owing to its simplicity, versatility and the degrees of freedom it offers, this potentially low-cost bottom-up nanopatterning process opens perspectives towards the integration of advanced light-trapping schemes in thin solar cells. ispartof: Optics Express vol:24 issue:2 pages:A191-A201 ispartof: location:United States status: published

Deep-level transient spectroscopy (DLTS) has been applied to high-temperature annealed n- and p-type Si wafers. The aim is to identify the deep levels responsible for the observed minority carrier lifetime degradation after thin-film transfer to a glass substrate. Anneals have been performed at 1150 °C in H2 or Ar. Care has been taken to avoid radiation defect formation during the fabrication of the Al Schottky barriers used for DLTS. It is shown that besides a change in the carrier doping density and profile, an annealing-induced electron trap at 0.43 eV below the conduction band edge can be found, which is related to a vacancy–impurity complex.

Crystalline Si (c-Si) technology is dominating the photovoltaics market. These modules are nonetheless still relatively expensive, in particular because of the costly silicon wafers, which require large thickness mostly to ease handling. Thin-film technologies, on the other hand, use much less active material, exhibit a much lower production cost per unit area, but achieve an efficiency still limited on module level, which increases the total system costs. A meet-in-the-middle is possible and is the object of this paper. The development of c-Si thin-foil modules is presented: first, the fabrication of the active material on a glass module and then the processing of the Si foils into solar cells, directly on module level. The activity of IMEC in this area is put into perspective with regard to worldwide research results. It appears that great opportunities are offered to this cell concept, although some challenges still need to be tackled before cost-effective and reliable industrial production can be launched. Copyright © 2012 John Wiley & Sons, Ltd.

Monolithic solar modules made from thin-film crystalline-silicon layers of high quality on glass substrates could lower the price of photovoltaic electricity substantially. This paper describes three different approaches that we are currently investigating to address the challenge to form high-quality crystalline-silicon layers on glass substrates. The SLiM-Cut approach is a wafering technique that results in 50-micron thick layers with a minimum of material loss. We show that crack initiation can be used as a means to better control the lift-off process. The epifree approach involves the lift-off of ultra-thin monocrystalline films formed by reorganization of cylindrical macropore arrays in silicon upon annealing. So far, films with a thickness of around 1 μm and very simple cells with an efficiency of up to 4.1% have been achieved. Finally, a seed layer approach is presented based on the epitaxial thickening by thermal CVD of monocrystalline silicon layers bonded on glass-ceramic substrates. Very promising cell efficiencies of 11% and Voc values of up to 610 mV have been achieved using a very simple and non-optimized cell structure.

In the quest for lowering the manufacturing cost of silicon solar cells, imec has been working successfully on two crystalline Si ‘thin-film’ cell concepts. In a first concept, a 20 µm-thin Si solar cell is epitaxially grown on top of a porous Si-based Bragg-type reflector which is electrochemically etched in a low-cost UMG Si substrate. Large area solar cells with efficiencies of 15.2% have been made, using (semi-)industrial processing tools. This clearly demonstrates that this cell concept has almost reached the stage of industrial application. In a second, longer-term approach, a 1–5 µm-thin, stand-alone mono-crystalline film is created based on the controlled annealing of an ordered macroporous silicon layer (the ‘Epi-free’ process). With this very thin Si layer, a simple proof-of-concept solar cell has been made exhibiting an efficiency of 4%. By optimizing the cell process in terms of light trapping and passivation, efficiencies over 15% can be expected from this technology.

This work initiates an investigation of the impact of high-temperature annealings on the material quality of reusable substrates for an "Epifree" solar-cell process, where the substrate itself provides the active layer of the cell. The minority-carrier lifetime of simple bulk wafers is monitored by photoconductance decay and the mechanisms affecting it are explored by deep-level transient spectroscopy. The lifetime is found to drop from the first annealing and then to stabilize to values sufficient for solar-cell application, at a minimum of 101 μs. The amplitude of this drop is strongly related to the wafer type (MCz or Cz) and no major recombination center could be identified as possible cause.

The “Epifree” process involves the lift-off of a high-quality monocrystalline film formed by reorganization upon annealing of cylindrical macropore arrays in silicon, and can thus provide high-quality silicon films without resorting to costly epitaxy. The challenge of this new process lies in etching controlled and regular pores in silicon in a cost-efficient way, and in developing a process compatible with the difficulty of handling a micron-thin material. Proof-of-concept cells have previously been achieved and this paper presents the latest progress, with a first development of thicker films and the inclusion of rear-side passivation. The energy-conversion efficiency of 1-µm-thin Epifree cells was improved from 2.6 to 4.1% by depositing a stack of amorphous silicon (a-Si) layers as rear-side passivation. The increase in Voc was, however, limited and bound to a drop in Jsc. The choice of a-Si was revealed to be unsuitable because of the thinness of the film and the presence of a full aluminum rear contact. The thinness of the film leads to a decrease in rear-side reflectivity by the a-Si absorption, and the aluminum, although not leading to crystallization, partly migrates inside the a-Si stack upon anodic bonding as shown by TEM. These factors indicate that an alternative surface passivation should be developed. In parallel to process developments, the material was thickened by modifying the macropore array dimensions, leading to a 2.4-µm-thick material over 1 cm × 1 cm areas. The efficiency of the next cells is expected to increase with this thicker material. Copyright © 2010 John Wiley & Sons, Ltd.

To answer the challenge of obtaining thinner silicon solar cells, we developed a technique based on the transfer of a thin layer of high-quality monocrystalline silicon to a foreign low-cost substrate. The transfer is enabled by the reorganisation of macroporous silicon at high temperature: driven by the minimisation of their surface energy, pores close and, in specific situations, merge to form a large single void, a few micrometers under the wafer surface. As demonstrated in this paper, the micron-thick film above it may be detached and used to process a solar cell. The difficulty of this approach lies in appropriately ordering the macropores, while its originality is to enable processing of a high-quality material directly from porous silicon. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

To answer the challenge of less expensive renewable electricity, the photovoltaics community is focusing on producing thinner silicon solar cells. A few years ago, in the field of silicon-on-nothing structures, micron-thick monocrystalline layers suspended over their parent wafer were produced by high-temperature annealing of specific arrays of macropores. Those macropores reorganise into one single void and leave a thin overlayer on top. Since this method may be an inexpensive way of fabricating high-quality silicon films, this paper investigates its potential for photovoltaic applications. In particular, we investigated if large surfaces can be produced and transferred to foreign substrates with this method. We fabricated basic solar cells, without rear-surface passivation, on 5 cm × 5 cm-large and 1-μm-thick films transferred to glass, that showed energy-conversion efficiencies up to 2.6%. These cells demonstrate the feasibility of the presented concept as a layer-transfer process for solar-cell application. After formation by annealing, the film is only barely attached to its parent wafer, but can still safely be handled provided that any abrupt gas flow or pumping to vacuum is avoided. After transfer and permanent bonding, the sample can be handled as any bulk wafer.

Thin layers of silicon for solar cells can be lifted-off from wafers by taking advantage of the property of macropores to reorganise at high temperature and, in specific conditions, to form a high-quality layer on top of an empty space. Those conditions need to be identified and this work focuses in particular on the annealing ambient composition. Its influence was investigated by scanning and transmission electron microscopy and by Fourier-transform infrared spectroscopy. Apart from hydrogen, which has been used in previous studies, argon was found to be also compatible with the reorganisation. This result points out that the presence of oxygen impurities may not be as deleterious as expected, but that those impurities complicate the set of reactions taking place during the high-temperature process.

The growth of well-defined regular columnar macropores under front-side illumination on medium doped n-type silicon has been investigated. The various morphologies observed, with branched or columnar pores, differ from those reported so far on substrates of both higher and lower resistivities. Unlike stated by the macropore growth model, current density is found to influence the pore growth rate. These observations indicate that, under the conditions used in this work, the pore growth is at the border between meso- and macroporous mechanism. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The integration of two-dimensional (2D) periodic nanopattern defined by nanoimprint lithography and dry etching into aluminum induced crystallization (AIC) based polycrystalline silicon (Poly-Si) thin film solar cells is investigated experimentally. Compared to the unpatterned cell an increase of 6% in the light absorption has been achieved thanks to the nanopattern which, in turn, increased the short circuit current from 20.6 mA/cm2 to 23.8 mA/cm2. The efficiency, on the other hand, has limitedly increased from 6.4% to 6.7%. We show using the transfer length method (TLM) that the surface topography modification caused by the nanopattern has increased the sheet resistance of the antireflection coating (ARC) layer as well as the contact resistance between the ARC layer and the emitter front contacts. This, in turn, resulted in increased series resistance of the nanopatterned cell which has translated into a decreased fill factor, explaining the limited increase in efficiency., Authors' post-print version

We study the light trapping in thin film crystalline silicon solar cells with a pseudo disordered structure. It presents the non-clustered holes of pseudo disordered structure exhibits a better performance than the square lattice design.

We present an improved process for free-standing monocrystalline silicon (FMS) thin film solar cells developed at IMEC. We demonstrate that a thick annealed porous layer, or the quasi-monocrystalline silicon (QMS) layer, incorporated into a two-side contacted thin film solar cell structure does not produce any considerable series resistance. The best cell so far exhibits a conversion efficiency of 12.6% with a fill factor of 75.7% for an active layer thickness of 20 μm. This cell process includes emitter formation by phosphorous diffusion, silicon nitride deposition for antireflection coating and front surface passivation, and 50-μm-thick annealed porous layer remained on the rear. Despite the expected small reduction in solar cell's efficiency, maintaining the porous layer in the device structure renders the processing and handling of the thin FMS film much easier, thus leading to a better yield and up-scalability. PC1D simulations show that a thick QMS layer can lessen the short circuit current density in some degree, depending on the active layer quality, thickness, optical confinement, etc., while the other cell parameters remain substantially unvaried; a 10% to 15% higher process yield is expected to be sufficient to reach a break-even between the two processes.

Introducing nanophotonics into photovoltaics sets the path for scaling down the surface texture of crystalline-silicon solar cells from the micro-to the nanoscale, allowing to further boost the photon absorption while reducing silicon material loss. However, keeping excellent electrical performance has proven to be very challenging, as the absorber is damaged by the nanotexturing and the sensitivity to the surface recombination is dramatically increased. Here we realize a light-wavelength-scale nanotextured monocrystalline silicon cell with the confirmed efficiency of 8.6% and an effective thickness of only 830 nm. For this we adopt a self-assembled large-area and industry-compatible amorphous ordered nanopatterning, combined with an advanced surface passivation, earning strongly enhanced solar light absorption while retaining efficient electron collection. This prompts the development of highly efficient flexible and semitransparent photovoltaics, based on the industrially mature monocrystalline silicon technology.

This abstract reports the light trapping improvement in a mono-crystalline silicon thin film photovoltaic stack with double texturations. Finite difference time domain optical simulations are performed to design double texturations assisted crystalline silicon solar cells. Simulations show that the double texturations patterned 1 µm thick c-Si solar cell stack would have an obviously increased integrated absorption of 87% when compared to a similar but unpatterned and smooth stack In order to fabricate such patterned stacks, an effective set of processes is developed based on laser holographic lithography, reactive ion etching and inductively coupled plasma etching. Optical measurements performed on the patterned stacks highlight the significant absorption increase achieved in the whole wavelength range of interest, as expected by simulation.