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International audience; This paper addresses the reliability on a novel trench-based Triple Gate Transistor (TGT) fabricated in a 40nm embedded Non-Volatile Memory (e-NVM) technology. In the studied device, two vertical transistors are integrated in deep trenches alongside the main planar transistor to build a TGT. The reliability of this device is investigated targeting the gate oxide degradation, that represents one of the major reliability issues in e-NVM environment. Gate stress tests are motivated by the possibility to use independently trench transistors and the main planar transistor. Thus, the reliability of each gate oxide needs to be studied separately to the others. Moreover, different DC and AC stress tests are performed and analysed to understand the degradation mechanisms effecting the TGT device.

This letter addresses the design, implementation, and characterization of a novel high-density Triple Gate Transistor in a 40 nm embedded Non-Volatile Memory technology. Deep trenches are used to integrate two vertical transistors connected in parallel with the main planar transistor. Thanks to the built-in trenches, the proposed manufacturing process increases the transistor width without impacting its footprint. The voltage/current characteristics of a planar MOS structure are compared with the features of the new Triple Gate Transistor. The new architecture provides an improved driving capability, with an on-state drain current twice as high as its equivalent standard MOS, combined with a lower threshold voltage, suitable for low-voltage applications. Finally, the gate oxide and junction reliability are validated over the operating voltage range.

2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), Singapour, 4-7 Oct. 2021; International audience; Phase change memory (PCM) device associated with Ovonic Threshold Switch (OTS) selector is a proven solution to fill the gap between DRAM and mass storage. This technology also has the potential to be embedded in a high-end microcontroller. However, programming and reading phases efficiency is directly linked to the selector's leakage current and the sneak-path management. To tackle this challenge, we propose in this paper, a new sense amplifier able to generate an auto-reference taking into account leakage current of unselected cell, including a regulation loop to compensate voltage drop due to reading current sensing. This auto-referenced sense, built on the charge-sharing principle, is designed on a 28nm FDSOI technology and validated through extensive Monte-Carlo and corner cases simulations. From the simulation results, our sense amplifier is demonstrated to be robust for an ultra-large range of sneak-path current and consequently for a large range of memory array size, suitable for embedded memory in high-end microcontroller.

This paper presents a junction reliability study on a new architecture of high voltage transistor with a double poly gate for Non-Volatile Memory (NVM) Technology. The experiments results are supported by TCAD simulations. The drain-bulk AC stress was performed on the new architecture and compared with the conventional demonstrating an important improvement in terms of reliability, for different bias conditions, taking advantage of its design architecture. Finally, process and design optimizations of the new architecture are presented.

This paper presents a novel high voltage vertical trench MOS transistor designed to be used in a Non-Volatile Memory (NVM) technology. Huge hump effect is demonstrated explaining some phenomenon observed during the AC stress. Quasi-static measurements are also reported showing that this vertical trench MOS transistor can be suitable for the use in an NVM environment. Finally, the AC stress reliability results demonstrate significant instabilities of both parasitic and main transistors. The comprehension is supported by TCAD simulations.

International audience; Nowadays, the study of physical mechanisms that occur during Flash memory cell life is mandatory when reaching the 40nm and beyond nodes in terms of reliability. In this paper we carry out a complete experimental method to extract the floating gate potential evolution during the cell aging. The dynamic current consumption during a Channel Hot Electron operation for a NOR Flash is a proper quantitative marker of the cell degradation. Here both drain and bulk currents are measured and monitored throughout the endurance tests. We coupled these characteristics with quasi-static measurements to correlate the cell degradation with an equivalent transistor. The final goal is to be able to split the physical effects of repetitive hot carrier and Fowler-Nordheim operations, typical of Flash memories, to extract the electrical parameters evolution on a simple equivalent transistor.

In this work, we present a method to find a correlation between the measurements on single 40nm embedded Flash memory cell, and the 512kB test chip electrical results. The bridge between these two structures is the cell array stress test (CAST). We are able to simulate the behavior of a 10kb and a 1Mb CAST structures. The parasitic resistances are taken into account, as well as, the test chip distributions for the modeling. The aim is to reduce the time of test obtaining preliminary information concerning the fabrication process and the memory yield at the parametric test level and before the electrical wafer sorting.

International audience; The reliability requirements of Flash memory become more and more challenging. Flash memory technology development needs test chips to allow large statistical studies and a product-like approach. In this paper, we present a methodology of bitmap analysis to extract and follow the intrinsic and extrinsic parameters of a 40nm eFlash technology during ramp-up. This methodology is, first, based on analog bitmap acquisition on 512kB test chip, followed by correction of spatial variabilities like peripheral circuits' influences, array organization impacts and process-induced effects, to extract supplementary cell electrical parameters such as threshold voltage, transconductance or programing window. Finally, such an analysis tool enhances the advantageous properties of a test chip, its large memory cell statistics and its product-like organization, to give more reliable data. It yields more information about intrinsic cell technology weaknesses and the best way to tackle them when integrated at product level.

International audience; In this paper the consumption of Flash Floating Gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances and reliability. We use a new dynamic method to measure the drain current absorption in order to evaluate the impact of different bias conditions, and to study the cell behavior. The programming window and the energy consumption are considered as fundamental parameters. Using this dynamic technique, three zones of work are found; it is possible to optimize the drain voltage during the programming operation to minimize the energy consumption. Moreover, the cell's performances are improved using the CHISEL effect, with a reverse body bias. After the study concerning the programming pulses adjusting, we show the results obtained by increasing the channel doping dose parameter. Considering a channel hot electron programming operation, it is important to focus our attention on the bitline leakage consumption contribution. We measured it for the unselected bitline cells, and we show the effects of the lightly doped drain implantation energy on the leakage current. In this way the impact of gate induced drain leakage in band-to-band tunneling regime decreases, improving the cell's performances in a memory array.

International audience; In this paper the impact of the endurance degradation on the programming window and the energy consumption of Flash floating gate memories is investigated. We use TCAD simulations to confirm, predict and explain the behavior we have observed in previous experimental studies. These simulations have been developed for 90nm technology node Flash floating gate memories, but they are fully compatible with highly scaled devices. The use of interface traps in the simulation enables to reproduce the increase in the drain current consumption and the decrease in the programming efficiency after endurance degradation. Moreover, we highlight the fact that after degradation the hot electrons energy and velocity are lower, decreasing the electrons injection in the floating gate.

International audience; In this paper we present the behavior of a single nonvolatile Flash floating gate memory cell when it is irradiated, from the backside, by femtosecond laser pulses. For the first time we show that the memory cell state can change using this type of stimulation. The measurements were carried out with an experimental setup with an ad hoc probe station built around the optical bench. We present the experimental results using different memory bias conditions to highlight the charge injection in the floating gate. Then, we study the cell degradation to check the state of the tunnel oxide and the drain-bulk junction. The aim is to understand the failure mechanisms and use this technique for accelerated reliability tests. Finally we report the experimental results achieved for different laser energies.

In this paper we propose a new non-volatile charge trap memory architecture implemented on 200mm wafer in 90nm technology node. The aim of this work is to investigate an alternative and scalable solution for embedded low energy applications. The Asymmetrical Tunnel Window (ATW) memory cell has been developed in order to improve the programming operation during a hot carrier injection. The main property of this device is the presence of an asymmetrical tunnel oxide thickness along the channel. This characteristics enables an improvement in terms of current consumption and injection efficiency with respect to the standard Flash floating gate memory cell. In this work we describe the fabrication process of ATW memory cell and, using a commercial TCAD simulator and experimental results, we demonstrate the good functioning of our device thanks to the increased control gate/floating gate (CG/FG) coupling factor. To conclude we confirm the reliability performances with the endurance experiments up to 100k cycles.

International audience

In this paper the impact of the endurance degradation on the programming window and the energy consumption of flash floating gate memories is investigated. Using a new measurement technique we characterized the evolution of the dynamic drain current during the channel hot electron programming through the cycling. This experimental method has been developed for 90 nm technology node flash floating gate memories, but it is fully compatible with the highly scaled devices. We define the programming efficiency as a new figure of merit to evaluate the performances of flash memories and we demonstrate why this decreases during the cell aging. Moreover we confirm that the efficiency optimization point varies with the cell degradation. Finally, with a complete set of measurements, we show that our experimental protocol enables the understanding of the role of defects generation on the programming efficiency of NOR flash memories for embedded low energy applications.

This chapter presents an overview of the charge trap, silicon nanocrystals and split-gate memory technologies, which are currently envisaged as promising solutions to solve the scaling issues of standard embedded Flash memory technologies. In particular, we will focus on the main features allowing improved performance and scaling perspectives. We will also discuss in detail the main key challenges of these promising emerging technologies with particular focus on reliability issues.

In this paper, the electrical instabilities of Inter Metal Dielectric (IMD) SiOCH are investigated. These instabilities concern leakage current between metal lines and dielectric breakdown. At room temperature IMD leakage current tends to increase with waiting time. At high temperature and without electrical stress, a defect recovering phenomenon occurs and leakage current decreases. Depending on the applied electrical field, different conduction mechanisms are activated. At low field, Ionic conduction predominates, whereas at high electric field, Poole-Frenkel conduction is predominant. Comparing data and simulation results, ion activation energy is estimated. Then, presence of alkaline ions in SiOCH is suggested as the cause of electrical instabilities. Finally, Time Dependent Dielectric Breakdown (TDDB) is modeled as a function of initial leakage current and stress voltage bias.

International audience; In this paper we propose to optimize the 1T silicon nanocrystal (Si-nc) memory cell in order to reduce the energy consumption for low power applications. Optimized Channel Hot Electron Injection (a 4.5V programming window is reached consuming 1nJ) and Fowler-Nordheim programming are analyzed and compared. The tunnel oxide thickness, Si-ncs area coverage and SiN silicon nanocrystals capping layer are adjusted to optimize the data retention and endurance criteria. We present for the first time the endurance characteristics of a Si-nc cell up to 10 6 cycles with a final programming window of 4V.

International audience; In this paper we propose the optimization of the programming operation scheme of Silicon nanocrystal (Si-nc) memories in order to reduce the energy consumption for low power applications. Using the program kinetic characteristics and a dynamic current measurement method, the programming window and the energy consumption during Channel Hot Electrons programming are deeply analyzed; evaluating ramp and box pulse with various gate and drain voltage biases. Finally the critical role of the tunnel oxide is evaluated to satisfy both retention and consumption requirements.

International audience; In this work, a detailed study of the physical mechanisms governing the Source Side Injection programming in ultra-scaled (down to 20nm) SiN split-gate memories is presented. Experimental measurements coupled to static and dynamic TCAD simulations are shown. In particular, we claim that adjusting the select gate voltage in moderate inversion allows for the optimization of the compromise between high electron injection and limited consumption. Then, we show that scaling the dimensions of the select gate can induce a higher consumption, while scaling the memory gate leads to lower programming energy (

International audience; The problem of energy saving has today a relevant importance, concerning in particular all the portable devices as smart phone, tablet PC, smart card and so on [1]. In order to improve the features of these products, particular attention is paid to energy consumption of Flash cells in memory arrays. In this work we investigated the Flash floating gate (FG) dynamic behavior during the channel hot electron (CHE) programming operation. After this, we propose a solution to optimize the energy consumption. The samples studied in this experimental work are Flash floating gate memory cells (embedded NOR flash process). The ONO inter-poly dielectric stack has an equivalent thickness of 14nm, while the tunnel oxide of 9.5nm is grown on a p-type silicon substrate. The width and length channel dimensions are varied as well as the channel doping dose (CDD) and the lightly doped drain (LDD) energy implantation. In Fig. 1 we show the effect of ramp (a) and box (b) gate pulses on the programming window (PW) and energy consumption (Ec). The experimental setup and the method to calculate the energy are shown in [2]. Using a box is possible to obtain a good window saving the energy and the programming time (tp), in despite of the drain current peak at the pulse beginning [3]. We performed the same experiments on the samples with different dimensions: (90x180)nm 2 , (70x160)nm 2 and (70x140)nm 2. Several tests are performed using the reverse body bias (Vb=-0.5V) with fixed drain potential (Vd=3.8V) to demonstrate that it is possible to optimize the programming pulse, minimizing the Ec if the PW=5V is kept constant (Fig. 2). The drain current (Id) peak can disturb the control circuits of memory array [4]; to avoid this we decided to use a ramp followed by a plateau in order to characterize the devices. The channel doping dose is a parameter that plays an important role concerning the drain current consumption during a CHE injection. In Fig. 3 we show the effect of channel doping dose variation during the programming operation. The results report the improvement of programming window and consumption energy if the CDD is increased. The channel doping dose variation produces also the threshold voltage shift [5], in this case an adjusting of sense circuits is needed for an industrialization contest. The gate voltage pulse (Vg) used to measure the Id is obtained adding the 1.5V/µs ramp and a 1µs plateau (inset of Fig. 3), the drain voltage is constant (Vd=3.8V). An important point to evaluate, for a NOR architecture memory array, is the bitline leakage (BLL), due to a Gate Induced Drain Leakage (GIDL) in band-to-band tunneling (BBT) regime, during the CHE programming operation [6, 7]. We performed the measurements on a cell where the control gate and the floating gate are short-circuited; all the geometrical parameters are kept constant. The gate terminal is biased with-3V, the drain with 3.8V and the body using-0.5V. This condition allows to measure the Id of a non-selected programmed cell. In Fig. 4 we show that the BLL decrease if the arsenic LDD implant energy is increased. In fact, as it has been verified by process TCAD simulation (Fig. 5), increasing the LDD implant energy, the profile of drain-body junction becomes more abrupt, so the electric field in this region decreases. It is important to find the trade-off between the BLL and the programming efficiency. In this work we investigated the effect of channel hot electron programming operation for a Flash floating gate memory cell, by ramp or by box. We have shown the gain in terms of consumed energy that is possible to reach adjusting the programming conditions and scaling the cell dimensions. Moreover we demonstrate the effect of channel doping dose to reduce the energy and improving the programming window. Concerning the implementation of a memory cell in a NOR array, a trade-off between the bitline leakage and programming current can be found engineering the lightly doped drain implantation.

International audience; In this work, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1 st time. Silicon nanocristals (Si-ncs), or silicon nitride (Si 3 N 4) and hybrid Si-nc/SiN based split-gate memories, with SiO 2 or Al 2 O 3 control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. The results are analyzed by means of TCAD simulations.

Non-Volatile Memories (NVM) integrating silicon nanodots (noted SDs) are considered as an emerging solution to extend Flash memories downscaling. In this alternative memory technology, silicon nanocrystals act as discrete traps for injected charges.Si-dots were grown by Low Pressure Chemical Vapor Deposition (LPCVD) on top of tunnel oxide. Depending on the pre-growth surface treatment, tunnel oxide surface may present either siloxane or silanol groups. SDs deposition relies on a 2–steps process: nucleation by SiH4 and selective growth with SiH2Cl2.In a context of technological industrialization, it is of primary importance to develop in-line metrology tools dedicated to Si-dots growth process control. Hence, silicon-dots were observed in top view by using an in-line Critical Dimension Scanning Electron Microscopy CDSEM and their average size and density were extracted from image processing. In addition, Haze measurement, generally used for bare silicon surface characterization, was customized to quantify Si-dots deposition uniformity over the wafer. Finally, Haze value was correlated to Si nanodots density and size determined by CDSEM.

We characterize SET operation in Phase Change Memories. A measurement procedure aiming to investigate resistance transition from amorphous to crystalline states is shown. Results give interesting insights on the crystallization process of GST material and a simple model is introduced. Crystallization process obeys to a constant energy law. Fast SET pulses require high power; slow SET pulses can be implemented in low power applications. Results may be used for an optimized design of memory cell operating conditions.