27 results on '"Umimoto, H."'
Search Results
2. Effects of end-of-range dislocation loops on transient enhanced diffusion of indium implanted in silicon
3. Analysis of As, P Diffusion and Defect Evolution during Sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach
4. Non-destructive inverse modeling of copper interconnect structure for 90nm technology node
5. A 3-dimensional process-simulator based on an open architecture.
6. The inverse-narrow-width effect of LOCOS isolated n-MOSFET in a high-concentration p-well
7. A 0.05 /spl mu/m-CMOS with ultra shallow source/drain junctions fabricated by 5 keV ion implantation and rapid thermal annealing.
8. Improvement of RSF for a statistical design of lithographic process.
9. High speed 0.1 /spl mu/m dual gate CMOS with low energy phosphorus/boron implantation and cobalt salicide.
10. A statistical critical dimension control at CMOS cell level.
11. A 0.18 /spl mu/m Ti-salicided p-MOSFET with shallow junctions fabricated by rapid thermal processing in an NH/sub 3/ ambient.
12. A 3-D BPSG flow simulation with temperature and impurity concentration dependent viscosity model.
13. SMART-II: a three-dimensional CAD model for submicrometer MOSFET's
14. Three-dimensional numerical simulation of local oxidation of silicon
15. A Three-Dimensional Dynamic Simulation of Borophosphosilicate Glass Flow
16. A Simulation Model for Wet Cleaning of Deep Trenches
17. A self-aligned retrograde twin-well structure with buried p/sup +/-layer
18. Numerical modeling of nonplanar oxidation coupled with stress effects.
19. SMART-P: rigorous three-dimensional process simulator on a supercomputer.
20. A 0.1 /spl mu/m CMOS with a step channel profile formed by ultra high vacuum CVD and in-situ doped ions.
21. Numerical simulation of stress-dependent oxide growth at convex and concave corners of trench structures.
22. A self-aligned retrograde twin-well structure with buried p/sup +/-layer.
23. Depth Profiles of Boron Atoms with Large Tilt‐Angle Implantations
24. Improvement of RSF for a statistical design of lithographic process
25. Impact of the reduction of the gate to drain capacitance on low voltage operated CMOS devices
26. Trench Isolation with Boron Implanted Side-Walls for Controlling Narrow-Width Effect of n-MOS Threshold Voltages.
27. Impact of the reduction of the gate to drain capacitance on low voltage operated CMOS devices.
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