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Impact of the reduction of the gate to drain capacitance on low voltage operated CMOS devices.

Authors :
Yamashita, K.
Nakaoka, H.
Kurimoto, K.
Umimoto, H.
Odanaka, S.
Source :
1995 Symposium on VLSI Technology Digest of Technical Papers; 1995, p69-70, 2p
Publication Year :
1995

Details

Language :
English
ISBNs :
9780780326026
Database :
Complementary Index
Journal :
1995 Symposium on VLSI Technology Digest of Technical Papers
Publication Type :
Conference
Accession number :
92108054
Full Text :
https://doi.org/10.1109/VLSIT.1995.520862