Search

Here we combine the features of SnOx and ZTO semiconductors to produce a high-performance ZTO/SnOx/ZTO TFT.

A new carbon nano-tube field-effect transistor (CNTFETs) based power efficient and robust 8T (PER-8T) SRAM cell is proposed to reduce sub-threshold leakage currents, data dependency by improving RBL swing due to which RSNM is improved. Leakage power is reduced by using only a single pull-up transistor with high Vt in storage latch. The half-select issue is eliminated because the proposed work uses a de-coupled read port. This CNTFET-based proposed PER-8T cell is analysed for performance parameters of power, delay, and stability and compared to 8T SRAM cells at 45 nm technology. All simulations are performed at a supply voltage of 0.9 V considering the Stanford virtual source CNTFET(VS-CNTFET) model. It shows that RSNM and WSNM are improved by 12.07%, 14.85%, 56% and 46.46%, 20.39%, 66.05% compared to single ended 8T SRAM cells available in recent literature. The effects of VS-CNTFET parameters such as dielectric material, temperature, oxide thickness, and carbon nano tube diameter values on hold power are analysed and best values are considered. The cadence tool is used for measuring all design metrics at room temperature of 25°C.

Though Current Mode Logic has excellent features like higher switching speed and reduced crosstalk due to small output swing, there exists numerous flaws such as static power dissipation, non-suitable for power-down modes and comparably higher design complexity of load resistors. To address the aforementioned worries, this article incorporates a dynamic current mode design approach having active load and controlled current source to configure an improved (2/3) dual modulus prescaler. Simulation results of the proposed circuit using Cadence Virtuoso platform for 90 nm CMOS at 1.2 V supply depict a power consumption of 2.517 mW when driven by a high frequency of 2 GHz. The phase noise and output noise are found to be − 147.001 dBc/Hz and − 181.7 dB at 1 MHz offset while it reads a self-oscillation frequency of 5 GHz. The variation tolerance of the design is proved via 5% skew-based simulation at all corners; whereas the correct functionality at 28 nm UMC justifies its scalability.

Phase noise, lock range, lock time, and power consumption are becoming the dominant performance parameters in a charge pump phase locked loop (CP-PLL) especially at high frequencies. Though the PLL is having several blocks, the voltage-controlled oscillator (VCO) is the most impactful block considering the above parameters. Hence, it has been a call for better designing using the MOSFETs of a VCO circuit for an efficient PLL for several decades. In this work a VCO circuit is designed which uses the sleepy stack transistors to reduce the leakage current and later the new VCO is incorporated the PLL. With a wide lock range, this novel PLL architecture promises to offer better phase noise lock time and power consumption. This is possible due to the low leakage current that is produced by the stack transistors in the VCO. To support the above claims, the PLL using current starved stack VCO is designed and simulated in 90 nm CMOS technology. The simulation results shows that the VCO exhibits a phase noise of −78.28 dBc/Hz @1 MHz offset frequency while the PLL incorporating the same VCO has a lock range of 1.3GHz–1.5GHz. The power dissipation of the PLL is 46.05 μW, and the figure of merit (FOM) of the PLL is calculated to be −91.75 dBc/Hz.

In this work, a detailed investigation of RF and linearity analysis of junction-less Gate All Around (JLGAA) MOSFETs through SILVACO TCAD device simulator have been demonstrated. The impact of different metal gate work functions on various RF parameters such as drain current, transconductance (gm), output conductance (gd), gate capacitances (Cgs and Cgd), transconductance generation factor (TGF), cut-off frequency (fT), intrinsic gain(Av) and Gain trans-conductance frequency product (GTFP) are investigated. Furthermore, the impact of different metal gate work functions(ωM) on various linearity parameters such as gm2, gm3, VIP2, VIP3, IIP3, IMD3 were also investigated. It is observed that lower value of metal gate work function is suitable for radio frequency integrated circuit (RFIC) applications.

In today’s world, semiconductor nanowire GAA-MOSFET devices have stimulated a lot of scientific research interest in the field of semiconductor. It has been observed as one of the strong and gifted structure for future generation nano-scaled devices and integrated circuits (ICs). Basically, the term nanotechnology is the key powerhouse of semiconductor device engineering and technology to produce and operate the materials at nano-meter scale (10−9 m or 1 nm) either by top-down approach where the bulk materials are converted to a group of nano particles (atoms) or by bottom-up approach where the single groups of nano particles (atoms) are converted to the bulk materials. Nanowire GAA MOSFET is considered as work horse in semiconductor industry due to great electrostatic controllability over the channel and tight coupling. This review article investigates the different structural designs of nanowire devices using nanotechnology approaches for future device applications.

Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These effects can be overcome by using gate and channel engineering techniques which will improve mobility of the charge carriers, thus eventually improving drain current and trans-conductance of the device. In this work, the speed of operation for DG MOSFET is improved by reducing the channel length where dual-material gate-stack is deployed to avoid the drain-induced barrier lowering (DIBL) and hot carrier effects. In the presented device, the metal closer to the source and drain has higher and lower work function, respectively which causes a significant decrement in the peak electric field at the drain side and so the SCEs. The carrier mobility is also increased due to enhanced electric field in the channel, near the source, caused by higher work function gate material which, in turn, increases the MOSFET’s driving current. The screening effect reducing SCEs and an increment in the acceleration of the charge carriers in the channel are mainly attributed due to higher and lower threshold voltage found near the source and drain, respectively.

CMOS integrated circuits consisting of MOSFETs have tradeoffs among their performance parameters. Hence they need minimization in those tradeoffs calling for multi objective optimization to yield a circuit with enhanced characteristics. To perform simultaneous optimization of the Phase locked loop (PLL) performances using an effective multi objective optimization technique saving the designer’s time and causing the near best performance is the motivation of this work. Though the designer can optimize the circuit in the netlist level, it is less effective and a time consuming iterative process and sometimes it is next to impossible for complex and nanoscale circuits with large number of MOSFET devices and interconnects. Performance parameters like phase noise, lock time and power consumption are optimized subject to the practical design constraints using an efficient multi-objective optimization technique, infeasibility driven evolutionary algorithm (IDEA) in a real time environment. Using design parameters like the channel length and width of the MOSFETs for optimal performance, the PLL is simulated for model validation. Significantly superior performance achieved by the designed PLL is demonstrated. The phase noise, average power consumption and lock time achieved here are −126.3 dBc/Hz at 1 MHz offset frequency, 1.523 mW and 50 nS respectively.

Silicon nanowire (SiNW) structures are the essential foundations of the next generation highly efficient and lowcost electronic devices because of their specific chemical, optical, and electrical properties. In recent decades, the production of pure Si NW arrays with the ability to tune the wire density and dimensions has been intensively studied. This paper demonstrates the performance of silicon nanowire (Si NW) array based cylindrical gate all around (GAA) MOSFET using quantum transport model in lower technology nodes. With an improvement in drain current and lower value of threshold voltage, the proposed structure is proving itself as one of the leaders in GAA MOSFET family. Again the study includes the effect of variation in gate voltage on the electrostatic potential of individual nanowires and the potential developed at the channel-source/drain interface. The improved ON current with superior electrostatic integrity due to silicon pillars is showing the possibility of this device towards future development in CMOS technology. Finally, the article includes the integration of nMOS and pMOS to realize the CMOS inverter for high speed and noise immune characteristics.

This paper presents the effects of manufacturing process variations on the phase-locked loop (PLL) performances like lock time, lock range and phase noise. At higher operating frequencies, due to p...

У роботі проведено симуляційне дослідження багатоканального польового транзистора з горизонтальним розташуванням каналів та круговим затвором (GAA MOSFET) з розрахунком розділення каналів. Моделювання виконується у низько-технологічних вузлах з урахуванням квантового ефекту. Ізолятор, який використовується в розглянутій моделі, є high-k діелектриком, що дозволяє зменшити масштаб пристрою. Детально досліджуються розділення кремнієвих каналів та його вплив на характеристики пристрою. Отримані таким чином характеристики, а саме струм стоку (ID), порогова напруга (Vth), крутизна (gm) та коефіцієнт перемикання (Ion/Ioff), порівнюються для різних розділень каналів. Крім того, детально вивчається струм витоку та пов'язаний з ним короткоканальний ефект, такий як підпорогове коливання (SS), та його залежність від розділення каналів. Покращене на 28,9 % значення струму включення при SS, рівному 70,34 мВ/дек, досягається для розділення каналів в 10 нм. Однак коефіцієнт перемикання 9,13e+08 отримано для розділення в 6 нм, що порівняно вище, ніж для розділення в 9 і 10 нм. In this paper, a simulation study is carried out for a multi-channel gate all around (GAA) MOSFET with channel separation calculation. The simulation is performed in lower technology nodes by taking the quantum effect into consideration. The insulator used in this model is a high-k dielectric, which allows the device to be scaled down. The separation between the silicon channel and its effect on device performance is investigated extensively. The performance thus obtained is compared with different channel separations in terms of drain current (ID), threshold voltage (Vth), transconductance (gm) and switching ratio (Ion/Ioff). Further, the leakage current and associated short channel effect such as subthreshold swing (SS) and its dependence on channel separation are studied in detail. An improved value of on-current of 28.9 % along with SS of 70.34 mV/dec is achieved for a separation of 10 nm. However, a switching ratio of 9.13e+08 is obtained for a separation of 6 nm which is comparatively higher than 9 and 10 nm separation.

Junction less field effect transistor, also known as JLFET, is widely regarded as the most promising candidate that has the potential to replace the more conventional MOSFET used in IC technology at the present time. These FETs are less likely to have short channel effects (SCEs) than devices with junctions, as shown by their remarkable subthreshold swing and drain induced barrier lowering (DIBL). Due to its gate coupling, the Gate-All-Around (GAA) JLFET is a better contender to uphold Moore’s law than other existing sub-22 nm device architectures and regular JLFET, which allows more precise channel tuning. In GAA device structure, SCEs are minimized in comparison to junctionless at the same node technology. Among GAA and JLFET at the same technology node, the SCE is kept to a minimum in GAA. Until now, none of the manuscripts have provided a comprehensive review of the various JLFET structures and modeling techniques for the analysis of their various device parameters in a single place. From device evaluation and application to qualitative & quantitative parameter analysis studies likewise subthreshold swing value, DIBL and switching ratio, this manuscript provides comprehensive information on the various structures of Junctionless and Gate-Around JLFETs in one place. Furthermore, the manuscript provides a brief overview of various device modeling techniques of JLFETs for enhancing the device’s characteristics and its application in various semiconductor industries. This manuscript will provide researchers with an overview of how to design future generations JLFET structures with improved performance and modeling simplicity.

In this paper the performance of Reverse T-Shaped Double gate Tunnel field effect transistor is investigated (RT-DG-TFET)with respect to different bio molecules for application as biosensor. The proposed device is built in order to overcome the limitations of short channel effects (SCEs) in MOSFET devices. The recent outbreak due to Corona virus demanded the requirement of a lable free, highly sensitive, quick and meticulous biosensor for the detection of SARS-CoV-2 virus. This device study records the lable free electrical detection of SARS-CoV-2 virus using RT-DG-TFET that detects the virus because of the electrical properties (dielectric constant) of different bio molecules like protein, biotin, air, strepta, APTES, DNA etc. These are studied by using different dielectric modulation techniques in biosensor application. The etched nano-cavity implanted under the gate electrode first immobilizes the SARS-CoV-2 virus, which is subsequently used to identify it. The sensitivity and different analog/RF parameters are also investigated for different bio molecules. All these simulations are investigated in TCAD Sentaurus simulator.

A novel Gate All Around Negative Capacitance Junction less FET (GAA-NC-JLFET) is proposed in this work, where different RF/Analog, Linear, and Non-linear parameters were investigated for different ferroelectric thickness in depth. The simulation result is calibrated with the available experimental data from literature. Adding a layer of ferroelectric material to a JLFET is a good means of decreasing short channel effects when compared to typical GAA JLFETs. The effect of ferroelectric layer thickness on DC parameters such as drain current (IDS), subthreshold swing (SS), threshold voltage (Vth), and Ion/Ioff as well as linear parameters such as transconductance coefficients (gm2 and gm3), voltage intercept points (VIP2 and VIP3), and input intercept point (IIP3) have been studied. Furthermore, this paper investigates non-linearity parameters such as harmonic distortion and intermodulation distortion in relation to various ferroelectric thicknesses. The TCAD device simulator was extensively used to conduct this analysis, and the results revealed that increasing the ferroelectric layer resulted in a significant improvement in the values of RF and linear parameters, as well as a decrease in the values of non-linearity parameter values, resulting in an increase in the device’s linearity, which can be used in wide range of RFIC applications.

In this paper, a nanotube architecture of Junctionless FET (JLFET) is investigated wherein it is observed that the performance characteristics of JLFET are improved by introducing Dielectric Pockets into the device near the source-channel and channel-drain interfaces by coming up with a novel structure of nanotube junctionless FET (NTJLFET) called as Dielectric Pocket-NTJLFET (DP-NTJLFET). Using TCAD tool, the proposed DP-NTJLFET has been simulated for a channel length of 20 nm in order to consider and show the improvement in various short-channel effects. The inclusion of Dielectric Pockets into the device significantly reduced the OFF-state current, which eventually improved the current switching ratio (∼2600%) for a pocket length and thickness of 4 and 7 nm, respectively. Further, the proposed device exhibits an improved subthreshold swing characteristics and a better measure of DIBL (improved by ∼12%) for DP-NTJLFET as compared to the conventional NTJLFET. As a result of achieving low OFF-state current, the proposed DP-NTJLFET may be found suitable for the future low-power applications.

In a continuous effort to keep the Moore’s law alive in lower technology node without deteriorating the device performance, several device engineering techniques are introduced. These engineering techniques involve channel engineering and gate metal engineering also. Evolution of Multi gate MOSFET devices from conventional planar structure to gate all around (GAA) is continuously going on. With unique design, GAA MOSFET is measured as one of the best devices for better electrostatic control. The threshold voltage of a device depends on the work function of metal gate electrode. This work introduced a linearly modulated work function (5eV-4eV) metal gate along z-axis. This work demonstrates the advantages of work function modulated metal gate on the DC performance characteristics in lower technology nodes. An improved drain current (Id) with lower threshold voltage (Vth) indicates the superiority of the device for future generation applications.

The latest electronic gadgets demand many functionalities which requires enhanced performance of the processor. To ensure this, cache based on Static Random Access Memory (SRAM) is a vital part in electronic devices. Above 90 nm technology, we can build an SRAM in CMOS LSI technology without electrical stability, by connecting six transistors. However, leakage and variability of transistors in SRAM cell have become dominating factor below 90nm technology. So we must design SRAM bit cell with utmost care. Recently SRAM cells have been designed to deal with these problems. However, it is an important task to achieve a balanced performance between all SRAM cell parameters of sub-nanometer technology. A new design of SRAM is presented in this paper to elevate the performance. The proposed SRAM is designed and implemented in CMOS 90nm technology and produces comparatively better performance in terms of Static Noise Margin (SNM), stability and power dissipation when compared with conventional 6T SRAM. The cell reduces the energy consumption by using the technique of stacking. The stability of proposed SRAM is also high compared to recent designs.

This work has been paying attention to design and implement a Transmission gate phase frequency detector (TG-PFD) for Fast locking and low Reference Spur PLL working in Giga-Hertz choice. It has been experiential that the projected TG-PFD could completely erase delay for reset thereby eliminating dead region and blind region as well. By inclusion of the transmission gate into the PFD, could enhance the magnitude of the output signal and hence could improve the loop band and obtained a PLL with reduced locking time. Leakage current minimized as a result of adding CMOS inverters at the output of the TG-PFD and thereby obtained better reference spur for the Phase Locked Loop implemented using TG-PFD. Reference Spur of −77.2 dBc, locking time of 2.83 µs have been obtained for the designed PLL using projected TG-PFD in 180 nm CMOS technology which is exactly matching with the mathematical analysis done by this paper.

This article proposes an analytic charge-based model that incorporates interface trapping. The model’s applicability to all operating zones includes various interface trap charges with varying doping concentrations. Using the analytical model, the impact of interface traps on different electrical parameters, such as channel potential, surface potential, electric field, and drain current, is examined. The transconductance and cut-off frequency models are also developed from the drain current model. To validate our model, the analytical model results were compared with the TCAD device simulation results and available experimental data from literature. The Fermi level location of interface traps greatly influences surface potential in the bandgap, leading to subthreshold deterioration and flat band shifting in Junction Less Field Effect Transistor (GAAJLFET) with SiO2 as a gate insulator, which leads to performance degradation of different device parameters. To decrease the impact of the interface trap on the device’s characteristics without impairing the performance, a suitable device with SiO2 and high-k gate-stack as an insulator is designed and compared with GAAJLFET with SiO2 as a gate insulator. A GAAJLFET with SiO2 as an insulating material has very different device parameters than a GAAJLFET with SiO2 and high-k gate-stack as a gate insulating material.

This work is a Raspberry Pi-based prototype that has been built while keeping both the Indian agricultural scenario and hobbyist backyard gardeners in mind. It aims not only to act as a solution to conventional method of growing plants but also to approach along the lines of sustainable development. With our project, we are also aiming to optimize the amount of resources required to grow a plant. The model acts as the brain of the plant by providing directions to the technical implementations of the setup such as an attached pair of wheels and a water pump to act according to the requirement. This prototype could be a possible solution to majority of the urban population planning to have potted plants and greenery in their apartment but with space, time and effort constraints. Further details like implementation, advantages and future are mentioned in the next sections.

This paper describes a continuous and almost linearly modulated work-function adjustment between 4.8–4.2eV using Hf-Mo binary alloy. The work-function modulated (WM) metal gate is applied to a gate all around MOSFET (GAA) for better electrostatic control. The threshold voltage is tuned by linearly modulating the gate metal work function. The threshold voltage extracted for dual-GAA MOSFET is initially 0.705 V. However, introducing work-function modulation, the threshold voltage is shifted to 0.620 V for WMGAA and 0.632 V for dual-WMGAA MOSFET. The simulation results validate the benefits of using work-function modulated metal gate in place of normal metal gate in terms of electron mobility, threshold voltage (Vth), and drain current (Id). An improved device performance with reduced short channel effect shows the capability of this device for various circuit applications.

The read instability of conventional 6T-SRAM cell has made the 8T-SRAM cell a substitute for high data reliability. But the single ended nature of read operation demands a complete Vdd swing of high capacitive read bit lines leading to large energy consumption. A novel assist technique using charge recycling concept is proposed here which reduces the read and write energy by reducing the voltage swing. Mathematical analysis of the proposed technique, theoretically predicts the read and write energy to reduce by 75% and 25% respectively compare to that of the conventional 8T-SRAM array. Experimental simulation using predictive technology model demonstrates these two energy consumptions to be reduced by 58% and 27% respectively. The proposed technique also reduces the leakage current flow in the standby cells and hence the energy consumption. The dummy read current flow in the half-selected cells is also controlled significantly in the proposed technique. The stability of the SRAM cell remains unchanged by the insertion of the proposed assist technique.

Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.72.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX.

In modern SOC design SRAM has become an integral part owing to its capability to form a bridge and overcome the speed mismatch problem between the high speed processor and the low speed data storage devices. Because of the read and write operation of SRAM cell having conflicting transistor sizing requirement, it is very difficult to maintain the transistor size to satisfy both the needs. The destructive nature of read operation enforces a serious thought about SRAM cell data stability. Transistor sizing and cell stability already being a critical problem becomes even more critical when we consider the process and temperature variation. Thus the SRAM should be designed with keeping the process and temperature variation in mind. The random fluctuation in device parameters such as transistor width, length, oxide thickness, oxide capacitance and doping concentration leads to variation in the threshold voltage and other transistor characteristics. The change in these transistor characteristics alters the SRAM cell performance. Hence this should also be taken care of to ensure the cell performance to be in the desired range even in presence of random fluctuation during fabrication process. The various performance measure such as SNM, write SNM, speed and power consumption must be tested under worst process corner as well over a wide temperature range to ensure that they lie in the acceptable range during worst operating condition. Also these parameters must be tested using Monte Carlo simulation to ensure a robust operation in presence of random fluctuation during fabrication process.