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The characteristics of the GaN based Vertical Light Emitting Diodes on Metal alloyed Substrate (VLEDMS) were investigated. The VLEDMS exhibits very good current-voltage behaviour with low average dynamic resistance of 0.7 Ω and low operated voltage of 3.2 V at 350 mA. High current operation up to 2000 mA in continuous mode was demonstrated without any performance deterioration. The high thermal conductivity of metal alloyed substrate demonstrated excellent heat dissipation capability. Chip scaling without efficiency loss shows a unique property of VLEDMS and enabled to enlarge up to 2 mm × 2 mm chip size. A light output efficiency of 70 lm/W or better was achieved in single chip or multiple chips package. Coupled with mass production ability, VLEDMS is very suitable for general lighting application. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

High power near-UV LEDs with the wavelengths ranging from 365 nm to 410 nm are released for the curing application. Owing to the superior design and the process technologies of the vertical LED on metal alloy base, the conventional mercury-based lamps can be replaced by the LED emitters providing higher reliability, longer life time, lower cost and the environmentally friendly benefits. Coupled with the silicon sub-mount package, the vertical LED can sustain very little UV output decay more than 1000 hours by the high power input of 2W-up. The external quantum efficiencies of 45% and 12% are achieved for the wavelengths of 410 nm and 365 nm, respectively, with the help of the vertical design to eliminate the current crowding issue and the optimal surface pattern to extract UV photons.

GaN vertical LED on metal alloy substrate (VLEDMS) is a desirable technology suitable for solid state lighting application from the viewpoint of reliability and lighting efficacy performance. A new top surface engineering technique for efficient light extraction is employed to VLEDMS to improve power conversion efficiency further. Corrugated pyramid shaped (CPS) surfaces are developed and formed on VLEDMS. By using such structure, VLEDMS exhibit a great enhancement of around 20% in light output power, and a high efficiency of over 100 lumens per watt can also be achieved by white LEDs. In the life test, the light output power of VLEDMS chips drop only by less than 10% within 3,000 hours, and the chips can also endure over 1000 cycles of thermal shocks without significant variations in electro-optical performance. Therefore, the highly reliable and bright VLEDMS using CPS surface engineering technique is very suitable for the solid-state lighting application.

Vertical GaN based Light Emitting Diodes on metal alloy substrate (VLEDMS) were realized and characterized for solid state lighting application. An efficiency of more than 100 lumens/watt from a white LED was achieved. And, an efficiency of more than 80 lumens/watt from a high efficiency and high power green LED was achieved also. The dissipate heat more effectively than conventional and flip-chip LEDs, thanks to the higher thermal conductivity of a copper alloy substrate. This increases their maximum operating current and output power and makes them more suitable for solid-state lighting applications. In addition, these VLEDMS exhibit many advantages over those on sapphire under extreme operation conditions for general lighting application.

GaN vertical LED on metal alloy substrate (VLEDMS) has been successfully realized for wavelength spectrum from near UV to green color. Owing to the vertical structure and highly heat-conductive metal alloy substrate, VLEDMS exhibits an ultra high brightness and excellent reliability suitable for solid state lighting (SSL) application. A brightness of 80Lm/W using 450 nm chip mixed with yellow phosphor was achieved by optimization of LED structure epitaxy, chip process and packaging. Using 405 nm chip with polychromatic phosphor a 50 Lm/W white light with color rendering index better than 90 was obtained. We also can get very good uniform correlated color temperature from package with VLEDMS chip.

In this paper we describe GaN based Vertical Light Emitting diode on Metal Alloy Substrate (VLEDMS) as a disruptive technology to solve the heat dissipation and current-crowding effect for the power device operated at high current. We focus on reliability features of VLEDMS under various operation regimes required for solid state lighting (SSL) application.

A double-layer metal (DLM) process having 2- mu m pitch for both metal levels has been successfully developed. This DLM system has been used in a 0.7- mu m CMOS process to fabricate 1-M SRAM and 256 K SRAM devices. Some relevant design rules are 1- mu m metal line and space for both levels, and 0.9- mu m contact and via openings. To meet these requirements, the process features planarization to minimize topology at LOCOS, polysilicon, and metal levels. The technological results are presented as well as reliability and electrical results. Photographs of fully processed and functional 256 K and 1-M high-performance SRAMs are shown. >

A high performance CMOS technology has been developed for application in very fast circuits. A 1 Mb SRAM with 6 transistor cells was designed /1/ end processed. Figure 1 shows a photograph of the completed chip. The insert is a magnification of the corresponding corner. In table 1 the most important design rules are listed with a summary of the technology and some data of the memory. The technology contains 0. 7 µm lithographic dimensions. Important features are: tight field isolation (1.0 µm) achieved by a special masking and oxidation procedure /2/, twin retrograde wells to provide high parasitic threshold and punch throughout voltages and an extremely small n+ to p+ spacing of 2. 5 µm. Latch-up is sufficiently suppressed by the use of thin p-/p+ epi material. The gate oxide thickness is 17.5 nm. Both n-channel and p-channel MOSTs contain an LDD structure. A strap technology is used to realize buried contacts and local interconnect. Ti salicide technology and double level metal offer a low resistance interconnect. Planarization is applied throughout the process.