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This paper describes orthogonal scaling of dynamic-random-access-memories (DRAMs) using through-silicon-vias (TSVs). We review 3D DRAMs including DDR3, wide I/O mobile DRAM (WIDE I/O), and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems. We then cover embedded 3D DRAM for high-performance cache memories, reviewing an early cache prototype employing face-to-face 3D stacking which confirmed negligible performance and retention degradation using 32 nm server and ASIC embedded DRAM macros. A second cache system prototype based on POWER7 was developed to confirm feasibility of stacking $\mu {\rm P}$ and high density cache memory, with $> 2~{\rm GHz}$ operation. For test and assembly, a micro-electro-mechanical-system (MEMS) probe-card with an integrated active silicon chip, realized a 50 $\mu{\rm m}$ pitch micro-probing at-speed-active-test for known-good-die (KGD) sorting. Finally, oxide wafer bonding with Cu TSV demonstrated wafer-scale 3D integration, with TSV diameters as small as 1 $\mu{\rm m}$ . The paper concludes with comments on the challenges for future 3D DRAMs.

For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS) embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation.

Novel device structures with vertical channels gated by TSV's are demonstrated. The unique device structure is realized in a standard TSV process flow, without new material systems or processes. They can be used for both characterizing the TSV process as well as enable new functions. They can be easily integrated into product designs thus enabling field monitoring.

High performance processors and ASICs typically require multiple voltages and multi-domain voltage controls across the die. Conventional approaches distribute the voltage regulation elements between the processor, the package laminate, and the printed circuit board. We propose an alternative approach where the voltage regulator is embodied in a 3D configuration such that the inductor, capacitor and the switches are formed on a separate silicon chip sandwiched between the processor and the laminate. Due to the close proximity of regulator to the processor, this approach can enable granular voltage domains, while minimizing disruptions to the processor layout. We describe a 4-f DC-DC buck converter fabricated on 32nm SOI wafers using TSVs to connect the switches on the front-side of the wafer to the inductors on the grind-side. The process builds on a 32nm SOI CMOS flow, adding deep trench (DT) capacitors and TSV's. Down conversion from a standard I/O voltage under various load conditions was evaluated, and an efficiency of 77% was achieved.

Through Silicon Vias (TSV) is a key enabler for interposer and 3Di technologies. As the TSV process integration is maturing, reliability is a key parameter to be studied. One such reliability wear-out mechanisms is electro-migration (EM). In this paper, we report on experimental electromigration studies of TSVs used in 3-Dimensional integration (3Di). While TSV themselves can carry large currents, the connection to on-chip wiring -- so called capture levels on both sides of the thinned die are the weakest link from an EM perspective. EM performance of the TSV element itself, the TSV/capture level and TSV/redistribution level (RDL) is investigated using dedicated structures with the respective elements as the weakest link. 300mm 3Di wafers were used using a 32 nm CMOS process with a 6 µm solid Cu TSV integrated at the fat wire levels and our results suggest that this integration scheme exhibits robust EM performance. With the right capture metallizations on both sides of the TSV, we estimate a DC current of 1A per TSV can be sustained for a 10KPOH product. Design methodologies to further improve and better redistribute the current to improve EM performance will be presented.

This study explores the reliability of a wireless sensing unit by testing it in a real-world university laboratory environment. The unit employs off-the-shelf products for their key components, while a flexible payload scheme was adopted for radio packet transmission to maximize throughput and minimize latency. The testing consists of two main parts: (1) a series of loopback tests using two off-the-shelf radio components with carrier frequencies of 900 MHz and 2.4 GHz, respectively, and (2) wireless transmission of a shake table response to a periodic swept sine excitation. The performance of the wireless channel is examined in each part of the study. Through this experimental investigation, it is validated that a loopback test may be used as a fast prototyping approach to characterize the complex transmitting environment of a structure in which a wireless monitoring system is installed. Various factors leading to signal attenuation are ranked according to their effects on packet delivery performance. Transmitting range and building materials are among the leading factors causing packet loss (and therefore data loss) in this specific testing environment. The severity of interference from 802.11b wireless systems in close proximity to the wireless sensing unit was investigated. Some preliminary results on the influence of operating rotating machinery and human activities are to wireless sensors were investigated. The results presented herein offer a guideline for applying wireless sensing within real-world structures so that the reliability of the wireless monitoring system is maximized. Due to uncertainties associated with the reliability of wireless communications, statistical analysis is performed on the collected time histories to reveal the underlying patterns associated with data loss. Temporal correlations of data loss were measured and found to be related to the adopted radio. A statistical distribution of the size of consecutive lost data points was further derived from the collected data. Such results have identified the need to further develop: (1) reliable communication protocols to reduce these losses in data and information, and (2) robust data processing and system identification tools to anticipate and explicitly handle any data loss. Copyright © 2007 John Wiley & Sons, Ltd.

In this study, Field-Programmable Gate Arrays (FPGAs) are investigated as a practical solution to the challenge of designing an optimal platform for implementing algorithms in a wireless sensing unit for structural health monitoring. Inherent advantages, such as tremendous processing power, coupled with reconfigurable and flexible architecture render FPGAs a prime candidate for the processing core in an optimal wireless sensor unit, especially when handling Digital Signal Processing (DSP) and system identification algorithms. This paper presents an effort to create a proof-of-concept unit, wherein an off-the-shelf FPGA development board, available at a price comparable to a microprocessor development board, was adopted. Data processing functions, including windowing, Fast Fourier Transform (FFT), and peak detection, were implemented in the FPGA using a Matlab Simulink-based high-level abstraction tool rather than hardware descriptive language. Simulations and laboratory tests were carried out to validate the design.

We integrated a copper TSV (Through Silicon Via) cell in a qualified 32SOI CMOS logic technology with high-K/metal gate and DT (Deep Trench) capacitors. Extensive wafer level characterization and reliability stressing were performed to evaluate the impact of the TSVs and 3D (3-Dimensional) integration processing on device and back end of line reliability performance. This included bias temperature instability stress, hot carrier injection, thermal cycling, wiring electromigration testing, and time-dependent dielectric breakdown studies. The integration of the TSV and process shows an equivalent reliability performance with respect to the 2D baseline for FEOL (Front End of Line) and BEOL (Back End of Line) structures within the assigned 3D design rules. In particular it is demonstrated that this TSV design allows BEOL structures at zero proximity to the KOZ (Keep Out Zone). Further, device and functional data indicate that there is no change in end of life reliability targets from TSV processing and/or proximity.

A new interaction between TSV processes and devices in close proximity, different from mechanical stress, is identified, studied and mitigated. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. An improved process is presented and confirmed in test structures and DRAM.

The method of solvent-enhanced dye diffusion for patterning full-color (red, green, and blue) polymer light-emitting diode displays was investigated in detail. After local dry transfer of dye onto a device polymer film, the dye remains on the surface of the polymer layer and must be diffused into the polymer for efficient emission. Exposure of the polymer to solvent vapor at room temperature increases the dye-diffusion coefficient by many orders of magnitude, allowing rapid diffusion of the dye into the film without a long, high-temperature anneal that can degrade the polymer. The increase in diffusion is due to absorption of the solvent vapor into the polymer film, which increases the polymer thickness and decreases its effective glass transition temperature Tg,eff. Measurements of the polymer in solvent vapor indicate that its thickness varies roughly linearly with pressure and inversely with temperature, with thickness increases as large as 15% often observed. A model based on Flory-Huggins theory is u...

We demonstrate an approach for fabricating nanometer-scale devices with minimal device areas while still retaining compatibility with integrated metal wiring. A self-aligned layer of silicon oxide evaporated on top of a thin (25 nm) gold film deposited on a substrate with an etched step ensures that only a fraction of the gold, along the step edge, is exposed. Self-assembled multilayers of 11-mercaptoundecanoic acid (MUA) were grown on the exposed gold to define an arbitrarily long device length. A second, evaporated gold layer served as second electrode. Devices with between 3 and 7 MUA layers were insulating, with currents that decreased exponentially with the number of MUA layers.

This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm 2 . Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 μm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.

For high-volume production of 3D-stacked chips with through-silicon-via (TSVs), wafer-scale bonding offers lower production cost compared with bump bond technology [1][2][3] and is promising for interconnect pitch

Differential thermal expansion mismatch between Cu and Si along with high aspect ratios required for TSV pose unique challenges to the integration and reliability of Cu TSV. A TSV structure that successfully mitigates these concerns has been integrated into CMOS with high K/metal gates. Data from test structures demonstrate no ‘Cu pumping’ or other deleterious effects to neighboring devices or interconnects. Functional 3D prototypes utilizing stacked embedded DRAMs were demonstrated showing no impact from TSV processing.

Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules. Thermal cycling and stress results show no degradation of TSV or BEOL structures, and device and functional data indicate that there is no significant impact from TSV processing and/or proximity.

CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demonstrated in 45 nm ground-rules at 1V and 200nA/mum off current for nFETs and pFETs, at a Tinv of 14 and 15 respectively. The drive currents were achieved using a simplified high-k/metal gate integration scheme with embedded SiGe and dual stress liners (DSL) and without utilizing additional stress enhancers. Devices have been fabricated with Tinv's down to 12 and 10.5 demonstrating the scalability of this approach for 32 nm and beyond.

To continue with the development of a wireless sensing unit built upon an off-the-shelf FPGA development board presented by the authors at SPIE 2005, this paper outlines a further effort consisting of embedding onboard computations, simulation and validation of the FPGA-based wireless sensing unit that is able to collect, process and transmit data. This research supports the concepts of decentralized wireless sensor networks and local-based damage detection, where individual wireless sensor nodes are capable of performing intricate tasks and can eventually transmit the processed results. An FPGA-based hardware platform is thus looked upon as a major contender for performing this function in a proficient manner. Throughout this research, the principal design complexities, in terms of both hardware and software development, are kept to a minimum. Development cycle and monetary cost of the hardware are other major considerations for this research. Data processing functions including windowing, Fast Fourier Transform (FFT), peak detection, are implemented into the selected FPGA, when limitations of different design options are explored to yield a solution that optimizes the resources of the selected FPGA. Numerical simulations and laboratory validations are carried out to scrutinize the operations and flexibility of the design.

This paper presents the preliminary results of an investigation on the application of Field Programmable Gate Arrays (FPGAs) to civil infrastructure health monitoring. An off-the-shelf FPGA development board available at a comparable price to microprocessor development boards is adopted in this study. Advantages, disadvantages, feasibility and design concerns when using such a reconfigurable hardware architecture for implementing algorithms for structural health monitoring in a wireless sensor unit are studied in a showcase of implementing Fast Fourier Transform (FFT) in a wireless data transmitting setting.

This paper presents the preliminary findings of a study on data and system identification results (derived from collected data) in a wireless sensing environment. The goal of this study is to understand how various hardware design choices and operational conditions affect the quality of the data and accuracy of the identified results; the focus of this paper is packet and data loss. A series of experimental investigations are carried out using a laboratory shaking table instrumented with off-the-shelf Micro-Electro-Mechanical Systems (MEMS) accelerometers. A wireless sensing unit is developed to interface with these wired analog accelerometers to enable wireless data transmission. To reduce the overall design variance and aid convenient application in civil infrastructure health monitoring, this wireless unit is built with off-the-shelf microcontroller and radio development boards. The anti-aliasing filter and analog-to-digital convectors (ADC) are the only customized components in the hardware. By varying critical hardware configurations, including using analog accelerometers of different commercial brands, taking various designs for the anti-aliasing filter, and adopting ADCs with different resolutions, shaking table tests are repeated, the collected data are processed, and the results are compared. Operational conditions such as sampling rate and wireless data transmitting range are also altered separately in the repeated testing. In all of the cases tested, data is also collected using a wire-based data acquisition system to serve as a performance baseline for evaluation of the wireless data transmission performance. Based on this study, the challenges in the hardware design of wireless sensing units and data processing are identified.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Thin (12-nm) self-assembled films of the insulating molecule 11-mercaptoundecanoic acid (MUA) were contacted by gold electrodes in a sandwich structure. Current-voltage scans of the resulting devices revealed symmetric negative differential resistance (NDR) with peaks at ±3 V and large peak current densities of up to 104 A/cm2. Devices could be programmed reversibly into nonvolatile high- and low-conductance states by applying 1-ms voltage pulses of 4 V and 10 V, respectively; this conductance could be probed non-destructively with voltages below 2.5 V. A conductance ratio of 103 between the high- and low-conductance states was measured. The NDR is attributed to the dynamic alteration of the device conductivity as the voltage is scanned. Devices fabricated with one gold and one aluminum electrode displayed NDR only for positive bias on the gold electrode, which supports a model in which the observed programming and NDR is due to the movement of gold in the film leading to the formation and destruction of conductive pathways through the insulating layer.

One promising method to pattern full color polymer Organic Light-Emitting Diode (OLED) displays is to print dye from a pre-patterned organic film onto a spin-cast polymer and then diffuse the dye into the film at room temperature in a solvent vapor environment. This method utilizes the well-known tendency for a polymer film to absorb solvent vapor, which depresses the glass transition temperature of the polymer and dramatically increases diffusion the dye. In this work, we have studied the temperature dependence of this process. The dye coumarin 6 (C6) was transferred onto films consisting of 2-(4-biphenylyl)-5-(4-tert-butylphenyl)- 1,3,4-oxadiazole (PBD) mixed with the polymer poly(9-vinylcarbazole) (PVK). Samples were then placed on a heated stage in a chamber and exposed to acetone vapor to diffuse the C6 into the polymer film. The profile of the diffused dye was determined by depthdependent photoluminescence measurements and Secondary Ion Mass Spectroscopy. We observed that the amount of diffused dye decreased at higher temperatures, in contrast to conventional thermally-driven diffusion. The results are understood by noting that the decrease in the polymer glass-transition temperature and the corresponding rapid increase in dye diffusivity depend on the quantity of solvent absorbed by the polymer, which decreases as the temperature of the polymer is raised.

Strain distributions within the active layer of a silicon-on-insulator substrate induced by through-silicon via (TSV) structures were mapped using x-ray microbeam diffraction. The interaction region of the out-of-plane strain, e33, from a TSV feature containing copper metallization extended approximately 6 μm from the TSV outer edge for circular and annular geometries. Measurements conducted on identical TSV structures without copper reveal that strain fields generated by the liner materials extend a similar distance and with comparable magnitude as those with copper. FEM-based simulations show the total interaction region induced by the TSV can extend farther than that of e33.

Thin (12nm) organic films consisting of self-assembled multilayers of 11-mercaptoundecanoic acid were contacted by gold electrodes. The devices could be operated as a programmable memory by applying low-voltage pulses to increase the conductivity by 103 and then high-voltage pulses to reverse the increase; the conductivity of the stored state could be read nondestructively by applying a still-lower voltage pulse. Programmed states remained stable for longer than three months and devices were functional for more than 104 programming cycles. Current-voltage measurements of the devices revealed negative differential resistance with enormous current densities characteristic of metallic conduction (up to 107A∕cm2). These results are promising for application in dense, high-speed memory arrays, where resistance-capacitance delays can be minimized by large current densities.