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Compressive Sensing (CS) is a promising technique for transmitting signals in power-critical applications such as Internet of Things (IoT) devices. Non-uniform CS optimizes this process by adjusting sampling frequency based on the relative importance levels characterized by the signal of interest. Recent advances have yielded energy-efficient hardware implementations of CS sampling, leveraging spin-based crossbar architectures for in-memory vector-matrix multiplication and through the use of probabilistic bit (p-bit) devices to generate tunable random outputs for writing the array. Thus, a region of interest is generated via column-ordered density of on-state devices. Herein, we propose a simple design for supplying inputs to the p-bit devices, based on Ohmic voltage attenuation occurring along the word lines of the crossbar array. The technique embeds some required computations to be conducted intrinsically by the cross-points of the memristive array, thus bypassing overheads of conventional instruction execution and eliminating the need for costly hardware components such as lookup tables and data converters. The design is shown to be robust for various array sizes and parasitics while generating the appropriate tuning signals within a single clock cycle duration of 1.6ns, and at an energy overhead of 333fJ. Compared with a standard approach using lookup tables and digital to-analog converters, the design herein achieves a 583-fold reduction in energy and 23-fold reduction in transistor count.

Thermometer-to-binary encoder is an essential part of a flash analog-to-digital converter (ADC). Errors in the thermometer code must be adequately handled by the encoder to avoid performance degradation. The presented concept of a reference encoder helps to classify errors and to compare error impact on real encoders. A new encoder structure is proposed as an alternative to the adder-based encoder known for its error robustness. Simulation in MATLAB reveals that the proposed encoder structure is as resistant to single and double errors in the input code as the adder-based one. Encoders were synthesized and simulated in 65-nm CMOS using Cadence design tools. For bit widths from 4 to 8, the proposed circuit is 10–12% larger in transistor count but has a 34–45% lower delay than an adder-based circuit which makes its use practical.

Ternary logic has been studied for several decades as it can offer significant advantages to reduce the number of interconnects and the complexity of operations. However, the excessive transistor count of the existing ternary logic gates can diminish these advantages in practice. In this brief, based on the negative capacitance (NC) feature of the ferroelectric materials and the well-proven electronic properties of the carbon nanotube field-effect transistor (CNTFET), we have proposed ultra-compact ternary logic gates. After developing a NC-CNTFET model, we have designed a 2-transistor ternary inverter, a 4-transistor ternary NAND, and a 4-transistor ternary NOR with the structures and transistor counts similar to the binary complementary metal-oxide-semiconductor (CMOS) logic. The simulation results ascertain the correct and robust functionality of the proposed ternary gates, even in the presence of process variations. Our proposed ternary inverter, NAND, and NOR gates lead to on average 65%, 60%, and 60% improvements in transistor count, 79%, 83%, and 77% improvements in the area, and 34%, 61%, and 54% improvements in energy-delay product (EDP) as compared to the previous state-of-the-art ternary gates. Our approach accentuates that the proposed ternary gates are the potential candidates for demonstrating more complex multi-valued arithmetic-logic units.

Due to the advancement of technology and the reduction in chip dimensions to achieve circuits with lower energy consumption, the design of fast integrated circuits with low power consumption has become very important. Approximate computing is one of the most attractive paradigms for reducing energy dissipation. In this article, a hybrid approximate 4:2 compressor and an imprecise multiplier with high speed and low power consumption are proposed. The suggested compressor has a very simple structure while providing an acceptable quality. The innovative design approach of the suggested hybrid approximate compressor simplifies the structure of the proposed imprecise multiplier and makes an excellent trade-off between energy efficiency and quality. The proposed designs are simulated using HSPICE with 7-nm FinFET technology. The simulation results indicate the superiority of the proposed approach regarding various performance parameters compared to the state-of-the-art counterparts. The hybrid compressor improves delay, power, power-delay product (PDP), energy-delay product (EDP), and transistor count on average by 35%, 67%, 77%, 83%, and 67%, respectively, compared to the other compressors. Furthermore, these improvements are 55%, 64%, 84%, 92%, and 60%, respectively, compared to the other approximate multipliers.

This paper presents a novel ultra-low power yet high-performance device and circuit design paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs (GOTFETs) and Carbon Nanotube FETs (CNFETs). One of the distinguishing novelty reported in this work is the introduction of an innovative GOTFET device, which exhibits more than double the on-currents $I_{on}$ and less than 1/10th the off-currents $I_{off}$ of equivalent, equally-sized mosfet s at the same technology node. Most of the ternary logic designs reported earlier in the literature encode ternary bits into binary for combinational functionality and then use an Encoder to get back ternary output. Unlike the earlier designs, this paper presents a novel and significantly more efficient approach of directly designing ternary logical functions with Low $V_{t}$ Transistors (LVT) and High $V_{t}$ Transistors (HVT) using CNFET and GOTFET technologies. The new approach simplifies the design and reduces the required transistor count & interconnects, thereby reducing the delays and power consumption. The proposed Ternary Half Adder (THA) circuit, designed using CMOS, enables a 52% reduction in transistor count compared to the conventional CMOS designs available in the literature. The THA implemented with CNFET exhibits 27 ps (87% lower delay than similar CMOS design and consumes 2.4 $\mu$ W power (11% lower than CMOS). On the other hand, CGOT THA exhibits 101 ps (51% lower delay than similar CMOS design) and consumes merely 1.26 $\mu$ W power (53% lower than CMOS, in ultra-low power regime). The overall decrease in the Power Delay Products (PDPs) are 88% and 77%, respectively, in the proposed CNFET and CGOT THA circuits compared to the CMOS THA.

Reconfigurable FETs (RFETs) are ambipolar transistors featuring the ability to conduct both electrons and holes, which is often achieved through the use of silicon nanowires or similar gate-all-around topologies. In this article, we present initial results for standard cell synthesis based on our planar RFET device, featuring top-down planar silicon based technology, lower fabrication complexity than nanowire approaches and a high operating temperature robustness. We first introduce the device physics by explaining the structure and the operating principle on device level. We also summarize recent device optimizations to increase drive current and achieve symmetry between N- and P-type conduction. Next to CMOS-style standard cells, we present a reduced transistor count XOR cell and analyze timing. Transient simulations are performed entirely in TCAD to accurately show device performance. Further we describe extraction of relevant parameters of these circuits for usage in synthesis tools and compare our standard cells to a similar 180nmSOI technology. Afterwards we perform timing analysis for a full adder and explore the boundaries of our device with a larger cryptographic accelerator core.

Despite the advantages of ternary logic, it has suffered from excessive transistor count and limited noise margin. This work proposes an ultra-efficient nonvolatile ternary flip-flop (FF) based on negative capacitance carbon nanotube field-effect transistors (NC-CNTFETs). By harnessing the negative differential resistance effect in NC-CNTFETs, the proposed design is similar to a conventional volatile binary FF regarding the number of transistors and control signals. During a scheduled power gating or a sudden power outage, the proposed ternary FF benefits from an auto-backup/auto-restore capability without employing any additional transistors, nonvolatile devices, or control signals. This leads to zero device overhead, which is a breakthrough in designing nonvolatile memory circuits. On the other hand, the back-to-back slave latch’s hysteretic behavior provides an extraordinary static noise margin that transcends the noise margin of both conventional ternary and binary latches. The simulation results indicate that eliminating additional backup and restore circuitries provides 43% improvements in transistor count, 59% improvements in power saving and 98% improvements in energy-saving than state-of-the-art binary and ternary FFs. Moreover, the proposed design presents a 1.5 times higher static noise margin than the conventional binary and ternary FFs. Our proposed approach opens new doors in realizing ultra-efficient nonvolatile ternary circuits and systems in neuromorphic applications using ferroelectric-based transistors.

In this article, the design fashion of high-speed 5-2 and 6-2 compressors along with their analysis, has been discussed. With the help of combinational logic consisting of the 4-2 compressor and 3-2 counter structures, a high-performance structure for 6-2 compressor has been obtained which shows significant speed improvement over previous architectures. The optimization is achieved by reducing the carry rippling issue between adjacent compressor blocks. Also, the proposed 6-2 compressor with some modifications will turn into a 5-2 compressor in which latency of the critical path has considerably been reduced, illustrating the superiority of designed circuits. The delay of proposed 5-2 and 6-2 structures is equal to 3.5 and 4 XOR logic gates, respectively, demonstrating speed boosting of 15% and 20% compared to the best-reported architectures. In addition, the power consumption and transistor count of proposed circuits are in reasonable level. Therefore, by considering the Power-Delay Product (PDP), our work will be a good choice for high-speed parallel multiplier design. Post-layout simulation results based on TSMC 90nm standard CMOS process and 0.9V power supply have been presented to confirm the correct functionality of the implemented compressors. These results have also been used as a fair comparison infrastructure between the proposed works and redesignated architectures of previously reported schemes.

Low power VLSI circuit design faces the challenging issues of static power dissipation as transistor count doubles for every couple of years. static power dissipation also known as leakage power dissipation which increases in scaled down threshold voltage circuits. Downsizing of CMOS innovation improved the speed and simultaneously leakage currents are left over as struggle. This unconstrained leakage current ought to be decreased for untroubled working of the circuit. This paper proposed novel static power reduction strategy with the literature survey. The research study mainly concentrated on circuit performance parameters like speed, power and power delay product of the specific circuit. This work presents logic gates designed and evaluated by mentor graphics tools with 22 nm CMOS Technology.

Memristor is dubbed as the fourth fundamental electrical component which works primarily as a non-volatile memory element. Memristors can also be used to construct logic gates, and Memristor Ratioed Logic (MRL) is one of these structures. The higher area efficiency and CMOS architecture compatibility of MRL gates have lead researchers to pay attention to its use in digital logic architecture. In this work, binary MRL is integrated with Complementary Metal-Oxide Semiconductor(CMOS) logic elements to develop building blocks of an Arithmetic Logic Unit (ALU). The proposed 1-bit ALU is simulated using LTSpice, which allows the versatility of changing the parameters as per the model used. This work designs and analyses an optimized cascadable 1-bit ALU with with voltage level based binary logic state via simulation. The proposed circuit shows improvement in transistor count and delay over benchmark circuits.

The design and implementation of digital systems with external configuration circuit–SHL (software–hardware–logic)—with standard cells based on floating-gate transistor (NeuMOS) and the implementation of the floating-gate potential diagram (FPD) to obtain Boolean functions are presented. External circuit configuration for designing digital systems of two and four bits reduces the number of transistors, as well as interconnection, and this can increase the speed of data processing; these results are helpful in growing applications like advanced driver assistance system (ADAS), where the number of sensors and processing time are increasing. Simulations results shown prove an effective reduction in transistor count, and a good performance of the system is demonstrated, as well.

PurposeThis paper aims to design three low-power and area-efficient serial input parallel output (SIPO) register designs, namely, transistor count reduction technique shift register (TCRSR), series stacking in TCR shift register (S-TCRSR) and forced stacking of transistor in TCR shift register (FST in TCRSR). Shift registers (SR) are the basic building blocks of all types of digital applications. The performance of all the designs has been improved through one of the metaheuristic algorithms named elephant herding optimization (EHO) algorithm and hence suited for low-power very large scale integration (VLSI) applications. It is for the first time that the EHO algorithm is implemented in memory elements.Design/methodology/approachThe registers together with clock network consume 18-36 percentage of the total power consumption of a microprocessor. The proposed designs are implemented using low-power and high-performance double edge-triggered D flip-flops with least count of clocked transistors involving transmission gate. The second and third register designs are developed from the modified version of the first one employing series and forced stacking, thereby reducing static power because of sub-threshold leakage current. The performance parameters such as power-delay-product (PDP) and leakage power are further optimized using the EHO algorithm. A greater reduction in power is achieved in all the designs by utilizing the EHO algorithm.FindingsAll the designs are simulated at a supply voltage of 1 V/500 MHz when the input switching activity is 25 percentage in Cadence Virtuoso using 45 nm CMOS technology. Nine recently proposed SR designs are simulated in the same conditions, and the performance has been compared with the proposed ones. The simulated results prove the excellence of proposed designs in different performance parameters like leakage power, energy-delay-product (EDP), PDP, layout area compared with the recent designs. The PDPdq value has a reduction of 95.9per cent (TCRSR), 96.6per cent (S-TCRSR) and 97per cent (FST in TCRSR) with that of a conventional shift register (TGSR).Originality/valueThe performance of proposed low-power SR designs is enhanced using EHO algorithm. The optimized performance results have been compared with a few optimization algorithms. It is for the first time that EHO algorithm is implemented in memory elements.

Energy dissipation in integrated circuits has become a matter of grave concern. Various approaches at different levels of abstraction such as logic-in-memory structures based on magnetic tunnel junction (MTJ) devices and approximate computing can be employed to reduce energy consumption. Efficient hybrid MTJ/FinFET designs for exact and approximate 5:2 compressors are proposed herein. The proposed designs use the spin Hall effect (SHE)-assisted writing method to store data in MTJs, which significantly improves the energy efficiency of the MTJ switching as compared with the conventional spin transfer torque (STT) method. The circuits are simulated in HSPICE using 7-nm FinFET and SHE perpendicular MTJ models. The results indicate that the proposed approximate designs provide significant improvements in terms of energy consumption and device count compared with their exact counterpart. The first and second proposed approximate designs improve the power consumption by 51%, read delay by 16% and 26%, and transistor count by 63% and 70%, respectively, as compared with the exact design. The second approximate compressor offers a significantly lower error rate (27% versus 48%) in comparison with the first approximate design, as well as better performance parameters. The imprecise 5:2 compressors are used in image processing applications to assess their accuracy metrics. Comprehensive MATLAB simulations indicate that the proposed approach provides great capabilities for image processing applications considering various accuracy and quality metrics.

In this paper, the design of ternary logic gates (standard ternary inverter, ternary NAND, ternary NOR) based on carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) is proposed. Ternary logic has emerged as a very promising alternative to the existing binary logic systems owing to its energy efficiency, operating speed, information density and reduced circuit overheads such as interconnects and chip area. The proposed design employs active load RRAM and CNTFET instead of large resistors to implement ternary logic gates. The proposed ternary logic gates are then utilised to carry out basic arithmetic functions and is extendable to implement additional complex functions. The proposed ternary gates show significant advantages in terms of component count, chip area, power consumption, energy consumption and dense fabrication. The results demonstrate the advantage of the proposed models with a reduction of 50% in transistor count for the STI, TNAND and TNOR logic gates. For THA and THS arithmetic modules 65.11% reduction in transistor count is observed while for TM design, around 38% reduction is observed. In this work, we aim to demonstrate the viability of RRAM in the design of ternary logic systems, thus the focus is mainly on obtaining the proper functionality of the proposed design. Also the proposed logic gates show a very small variation in power consumption and energy consumption with variation in process parameters, temperature, output load, supply voltage and operating frequency. For simulations, HSPICE tool is used to verify the authenticity of the proposed designs. The ternary half adder, ternary half subtractor and ternary multiplier circuits are then implemented utilising the proposed gates and validated through simulations.

The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.

One of the major concern for CMOS technology is the increase in power dissipation as the technology node lowers down to deep submicron region. Magnetic tunnel junction (MTJ) working on Spin transfer torque (STT) switching mechanism is recognized as one of the most promising spintronic device for post CMOS era due to its non-volatility, high speed, high endurance, CMOS compatibility and mainly the low power dissipation which can offer the solutions for the problems posed by existing CMOS technology. We have proposed a novel logic-in-memory (LIM) architecture of magnetic arithmetic logic unit (P-MALU) based on hybrid STT-MTJ/CMOS circuits. Simulation results reveal that there is significant reduction in the total power dissipation and transistor count of arithmetic unit by 28.44% and 29.16% compared to double pass transistor logic based clocked CMOS ALU design (DPTL-C2MOS-ALU), while 58.87% and 45.16% to modified magnetic arithmetic logic unit (M-MALU) respectively. Reduction in average power dissipation for logical unit is 37.61% and 52.55% along with 47.22% and 42.42% fewer transistors than DPTL-C2MOS-ALU and M-MALU design respectively. Monte-Carlo(MC) simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ, to study the behavior of DPTL-C2MOS-ALU, M-MALU and P-MALU designs in terms of power dissipation. All the simulation results reveal that the P-MALU is superior than other two ALU designs in terms of power dissipation, delay and device count. Further, the P-MALU circuit is extended for 4-bits arithmetic operations. Electrical simulations are performed to verify the functionality of the design for higher bit operations which demonstrates the feasibility of the proposed design in VLSI circuits.

In VLSI digital design, the Propagation Delay, Power Dissipation and Area of circuits are strongly related to the number of transistors which are present on an IC. Hence transistor optimization is special interest when designing digital integrated circuits. Therefore, efficient algorithms are used to generate optimized transistor networks, which are quite useful for designing digital integrated circuits (ICs). Several methods have been proposed for generating and optimizing transistor networks. Most Traditional solutions are based on factoring Boolean expressions in which only Chain - Parallel (CP) arrangement of transistors can be obtained from factored forms. Whereas grid-based methods are able to find CP and also non - CP (NCP) arrangements with potential reduction of transistor count. This method is an effective way of improvising VLSI circuits. In this an efficient algorithm is proposed i.e. Novel (Seed) method. It is automatically generates networks with minimal transistor count starting with irredundant sum of products (ISOPs) as inputs. Novel method is able to deliver both CP switching networks and NCP switching network arrangements, which improves VLSI circuit’s performance in terms of area, power and delay. All the network circuits are implemented in ASIC Cadence by using 45nm and 90nm technology with GPDK libraries. By using Cadence Virtuoso tool, it can obtain schematics of design and its test bench, power analysis, SPICE simulation and its simulation waveform.

This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications.

Flip-flop is one of the essential elements of data path structure design in the digital era. In this paper, the peculiar Flip-flop topologies, called as Conditional Pass Logic Static D-Flip-Flop (CPLSDFF) and Conditional Pass Logic Dynamic D-Flip-Flop (CPLDDFF) are proposed. The main objective of the proposed system is to optimize the primary performance criterions such as area and power. The first parameter is attained by reducing the device count, and the later is achieved by removing the redundant transistor switching, charge sharing and frequent power consumption from the source. The CPLSDFF and CPLDDFF are designed using SPICE with 130 nm IBM transistor technology and it shows that the silicon area is reduced up to 27% and 22% respectively. The conditional pass-transistor logic method is introduced in the proposed system leads to minimizing the unnecessary switching activity, charge sharing in intermediate nodes and power utilization is also minimized up to 12% in the static model, 70% in the dynamic model. The various performance parameters like transistor count, the clock driving power, data driving power, switching activity and propagation delay (D-Q) of the Flip-flop are investigated in detail and are correlated with the existing designs. The optimized CPLFF structures are also employed in 8-bit serial in serial out (SISO) shift registers and can save power up to 35% and 42% respectively. The outcomes show that the proposed system is most adaptable for low power applications with superior performance in register designs.

Using multi-valued logic (MVL) can reduce chip connections, which can have a direct effect on the chip area and connections power consumption. In the recent years, due to the high capability of nanotechnology in designing MVLs, some researchers have focused on this field. In designing MVL circuits, the low-complexity design is of great importance to fulfill the MVL aim. In this paper, a very low-complexity comparator for the MVL is proposed based on the multi-threshold voltage in CNTFETs. The proposed comparator in the 1-bit greater function only needs four transistors for all multi-valued logics; this results in a considerable transistor count reduction in comparison with the pervious works relying on 32 and 50 transistors in a ternary to quaternary case, respectively. Also, the number of 1-bit comparators is reduced from 50 and 74 transistors for the ternary to quaternary cases in the previous works to 12 in the proposed design. Additionally, the multi-digit comparator using the novel digit comparator is proposed. The simulation results using the Stanford 32 nm CNTFET library in HSPICE confirm the proper operation of the proposed comparator with the same range in PDP, in comparison with the previous works.

A large set of ASICs uses much more transistors than its necessity, as they use a library of cells with a limited amount of logic functions. This small number of logic functions in a traditional cell library represents an inherent limitation in the optimization of the number of transistors. In modern technologies, static power consumption is related to the number of transistors. To reduce leakage power, it is necessary to optimize the number of transistors. Therefore, it demands the use of a library-free physical design approach, using tools to allow the automatic layout synthesis of any transistor network. The goal of this paper is to present a new method to optimize the logical netlist, willing to reduce the number of transistors and connections, as well as the number of vias. Post-processing of the original logic netlist generated in a traditional design flow is completed, and a set of basic cells is replaced by just one new equivalent logic gate, thus simultaneously reducing the number of transistors. The connected cells of unitary fanout are considered to be merged into a new complex gate (usually not available in a traditional cell library). This approach is capable to reduce the number of transistors of a circuit by 21% on average when compared to the traditional solution, and by 4% when compared to other logic minimization tools. This provides an important leakage power reduction.

Reversible logic is an emerging digital design paradigm which promises low energy dissipation; thanks to its information-lossless nature. True potential of this exciting concept can only be assessed by facing the design of practical complexity applications. Low density parity check (LDPC) decoding is one such application from forward error correction domain. The core of LDPC decoding is the check node (CN) processor, which executes the decoding algorithm and constitutes a major portion of decoder's overall power consumption. This work proposes a low-power LDPC CN architecture using reversible logic gates. Transistor level design and full custom layout of proposed architecture is carried out on UMC 90 nm complementary metal–oxide–semiconductor technology. All reversible blocks of proposed CN are optimised for quantum cost, garbage outputs and transistor count. The CN functionality is validated with post-layout simulations, layout versus schematic checks and design rule checks. The proposed CN occupies a post-layout area of 0.013 mm2, achieves up to 4.3 GHz frequency and consumes 52 μ W power. The performance of proposed CN is also compared with its implementation using irreversible gates. The proposed CN achieves about 300% reduction in power delay product with affordable complexity as compared to its classical implementation.

This paper presents possible designs for high speed error tolerant adder using Gate Diffusion Input (GDI) technique. The 1-bit modified full adder (MFA) proposed in [1] is implemented using GDI technique (GDI-MFA). The GDI-MFA is extended to implement a 16-bit high speed error tolerant adder (GDI-HSETA). The performance of various configurations is studied based on metrics such as delay, area and power dissipation. The circuits have been simulated using pSPICE software. From the results it is observed that the proposed GDI-MFA has 52% less transistor count and consumes 33% less power compared to conventional adders. Results of simulation of GDI-HSETA and other adders in pSpice indicate that the proposed adder has 21.6% power reduction and 13% less transistor count. Also, based on the implementation of GDI-HSETA and existing 16-bit adders on FPGA Spartan 6 platform, it is observed that GDI-HSETA achieved power reduction compared to 16-bit adders using conventional design.

This research paper reports on a floating memristor model with minimum metal–oxide–semiconductor field-effect transistor count. The proposed structure uses only three nMOS transistors with a constant current bias and a single external capacitor. It offers less design complexity as compared to other existing memristor designs. The heart of the proposed design incorporates a MOS-based feedback circuit as an electronically controlled element for the memristance value. The memristor model has been integrated with 0.18- $\mu \text{m}$ Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) CMOS parameter. The pinched hysteresis loop of memristor for different frequency ranges and their composite characteristics are well analyzed using PSPICE simulation. The operating frequency range of the reported memristor is suitable up to few megahertz range. In addition to that application of the proposed MOS-memristor model is well described that comprises a Op-Amp-based Schmitt trigger circuit, a high-frequency modulation scheme, and an associative learning process. Finally, the postlayout simulation and experimental results are presented to validate the workability of the proposed memristor model.

For decades, computing logic uses Binary circuits based on CMOS technology. Ternary logic provides an edge over traditional Binary logic due to its ability to process more information content, thus reducing the Interconnection Count. In this paper, design of two Ternary D Latches based on GNRFET, are presented. Pass transistors along with STI gates are used to form the Ternary D latches (TDLs). These latches are cascaded in order to make Ternary D Flip-Flop (TDFF). The design is simulated on HSPICE, considering the three ribbon, 16-nm GNRFET model present on the Nanohub website. There is a considerable reduction in Transistor count as compared to the prevailing designs. Further, in our design, Propagation delay is also reduced significantly.

In this paper, a highly efficient ALU architecture is designed using Carbon Nanotube Field effect Transistor(CNTFET) and conventional MOSFET. High performing Multiplexer (Mux) based full adder is used for this purpose. First the performance of Transmission gate(TG) based Multiplexer and Pass transistor logic(PTL) based multiplexer are compared. Extensive performance analysis of several low transistor count hybrid adders has been done based on their power, delay, and PDP and thereby establishing Mux based Full Adder(FA) as the more efficient adder topology. The 4 bit ALU is implemented using the Mux based adder and its performance is compared with its CNTFET implementation. All the simulations are done using Cadence Virtuoso by 45nm technology for MOSFET and 10nm technology for CNTFET at 27°C for a supply voltage range of 0.6V to 1.2V. The CNTFET based circuits were designed to appraise their compatibility with conventional transistors and show considerable performance improvement.