Analysis of Static Power Reduction Strategies in Deep Submicron CMOS Device Technology for Digital Circuits

Low power VLSI circuit design faces the challenging issues of static power dissipation as transistor count doubles for every couple of years. static power dissipation also known as leakage power dissipation which increases in scaled down threshold voltage circuits. Downsizing of CMOS innovation improved the speed and simultaneously leakage currents are left over as struggle. This unconstrained leakage current ought to be decreased for untroubled working of the circuit. This paper proposed novel static power reduction strategy with the literature survey. The research study mainly concentrated on circuit performance parameters like speed, power and power delay product of the specific circuit. This work presents logic gates designed and evaluated by mentor graphics tools with 22 nm CMOS Technology.