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In this paper we explore for the first time the impact of an ultra-thin BOX (UTBOX) with and without ground plane (GP) on a 32 nm fully-depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50 mV DIBL reduction by using 10 nm BOX thickness for NMOS and PMOS devices at 33 nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299μm2 SRAM cell while maintaining an SNM of 296 mV@Vdd 1.1 V.

In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX (Buried Oxide) thicknesses with or without ground plane (GP). With a simple high-k/metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well suited for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk 45 nm technology in terms of variability and noise. A 0.499 μm2 SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1 V.

We present here a simple analytical model of the subthreshold slope of CMOS devices that successfully describes the long-channel plateau, the initial improvement for medium gate lengths, and the final degradation for short gate lengths. The model is based on the voltage-doping transformation (VDT) that leads to a new term in the subthreshold slope expression, explaining the degradation of the slope at very short channels. The potential minimum at the virtual cathode was expressed using a semiempirical expression that allows our model to fit to data that were extracted from simulation in a wide range of device parameters. Finally, the new slope model successfully reproduced experimental data that were measured on devices based on 90- and 65-nm technologies, demonstrating the validity of our model for advanced bulk CMOS technologies.

The carrier freeze-out is responsible for a kink-effect near the flat-band voltage in MIS capacitance-voltage (C-V) characteristics. By studying this phenomenon in depth, it has been demonstrated that the flat kink situation is governed by only two universal and constant parameters. Taking advantage of this particularity, a new method has been proposed and experimentally validated, aimed at extracting directly surface doping concentrations and impurity ionization energies.

In this paper we explore the impact of the parasitic bipolar in undoped channel Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32 nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The static parasitic bipolar latch occurs at a drain bias superior to the circuit operation alimentation. The several type of ground plane and forward or reverse back biasing do not modify significantly the bipolar breakdown voltage. The thicker EOT gate oxide is more sensible to parasitic bipolar breakdown. Finally, results have been reinforced by using calibrated TCAD simulation tool.

The paper analyzes the phenomenon of snapback (negative resistance region of the output characteristic) in MOSFETs. It shows that the expansion of the base of the parasitic bipolar transistor with drain bias provides the necessary basis for the understanding of the snapback mechanism. The R sub bottoming-out, resulting from the expansion, and the association of this phenomenon with the triggering of snapback is shown to be here a key point. This result may have some important practical implications since it not only provides simple criteria for the snapback triggering and sustaining (lacking to date) but also hints on how to shift the snapback towards higher drain bias.

The thesis of this paper is that the mechanism of multiplication-induced breakdown is essentially different from what has previously been thought. Two consecutive phases of the breakdown: enhanced body effect (EBE) and parasitic bipolar action have to be distinguished. It is shown that the difference between the EBE and the ordinary body effect results from the fact that the body effect does not involve any electrical field, whereas EBE has to account for a nonzero field in the bulk, necessary to drive the substrate current. Similarly the bipolar action may be treated in terms of a parasitic bipolar transistor, but only on condition that the variable geometry and unconventional mode of biasing of the base are taken into account. It has been found that the size of the base increases considerably with V DS . In addition, the base bias V be is not equal to V sub − V sub = R sub I sub becomes entirely constant) but rather to V sub + δΨ − V SB , where δΨ has been explicitly related to the substrate current I sub . The new physical model of multiplication-induced breakdown has been verified and confirmed according to numerical simulation results. Furthermore, the analytical predictions based on it agree very closely with measured drain and substrate current characteristics.

In this work, we report on the integration of 30nm gate length CMOS devices fabricated using laser spike annealing (LSA). Considerably improved short channel effects and drive current (+10% Ion at constant Ioff for NMOS) are demonstrated on samples using LSA. Excellent IonIoff characteristics (Ion = 940 muA/mum Ioff = 200 muA/mum for NMOS and Ion = 390muA/mum Ioff = 50 nA/mum for PMOS at Vdd = 1 V) are measured that are at the leading edge of the state of the art. Moreover, an enhanced dynamic behavior (-6% in ring oscillator delay) and improved characteristics of high density SRAM bit-cells (+24% Icell for the same 1sb) are reported. These results demonstrate the potential of LSA in the perspective of 30 nm device integration of a 45 nm bulk CMOS platform

In this paper, we present an innovative way of fabricating CMOS transistors with totally Ni-silicided (Ni-TOSI) gates without using a CMP step before the full gate silicidation. The combination of the use of a hard-mask-capped ultra-low Si gate with a selective S/D epitaxy step enables us to obtain a well-behaved silicidation of the junctions and the full gate within one single step with minimal gate lengths of 40nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.

In this paper, we present electrical results on damascene CMOS devices containing a HfO/sub 2/ gate oxide and a TiN/W gate electrode and give a detailed analysis of the performance data and the carrier mobility in both pMOS and nMOS devices. We report on an improvement of the electron mobility compared to recent literature data, which seems to be related to a slightly higher interfacial oxide layer. These findings are very interesting regarding the definition of a good trade-off between mobility and EOT for future CMOS transistors using high-k materials for the gate oxide.

It is shown that the physics of multiplication-induced breakdown (MIB) is essentially different from what has previously been thought. Two phases, multiplication-enhanced channel injection (MECI) and multiplication-induced bulk injection (MIBI) of the increased source injection, are distinguished. They are both shown to be impossible to treat conventionally. It is found that MECI can be accounted for in terms of a certain multiplication equivalent threshold lowering (METL). The latter, however, cannot be replaced by the body effect resulting from the external positive bulk bias equal to the internal self-biasing V/sub sub/=R/sub sub/I/sub sub/, as might seem desirable at first sight. In addition, although MIBI can be treated in terms of a parasitic bipolar transistor action, the mode of biasing of the latter, contrary to what other approaches postulate, has little to do with V/sub sub/. This is because of the substrate current I/sub sub/ which implies that the Fermi level follows the increasing (from the bulk terminal to the surface) potential. As a result, the source injection is considerably weaker than in conventional diode and can be associated with an effective junction bias which is much smaller than V/sub sub/. >

A majority of the proposed up-to-date negative resistance (N.R.) elements, being based on resonant tunneling or other quantum effects, lack compatibility with the silicon VLSI process. This work thus proposes two novel, not only silicon, but even more desirable CMOS compatible, N.R. Structures. The first is obtained by slightly modifying the vertical bipolar transistor, commonly used in BiCMOS technologies. The second is a hybrid device consisting of a 3-D co-integration in an SOI film of two separately operational devices: a lateral bipolar transistor and an accumulation mode MOSFET. When activating simultaneously both transistors, this same structure also exhibits the N.R. characteristic. >

Varied advanced architectures for 0.18/0.12 CMOS are investigated experimentally. Performances of heavy ion implanted, epitaxial and/or SiGe channels are compared through their electrical and physical characteristics. Conclusions on optimal 0.18/0.12 /spl mu/m channel architectures are drawn with respect to different applications. Very promising transport properties in SiGe channels are reported.

A long distance roll-off, occurring on Indium-doped NMOS architectures, is experimentally observed and analyzed. It is suggested that Indium is prone to a local interstitial-assisted deactivation in the junction vicinity. This interpretation is consistent with the results of material-, device- and modeling-oriented experiments. In order to recover good electrical performances, it is shown that Indium deactivation has to be reduced thanks to an interstitial-free process.

It is shown that punchthrough (pt) in very short buried-channel P-MOSFETs cannot be suppressed by diminishing the p-channel thickness t/sub c/. This is because of the drain-induced channel enlargement (DICE) effect, which switches on and becomes the dominant pt mechanism for very short channels. The DICE effect is independent of t/sub c/, and therefore the DICE-related pt component flows even with t/sub c/ to 0, so that strategies other than channel thinning are needed for the pt to be suppressed. A new implant step, called the retrograde implant, together with the LDD (lightly doped drain) structure, is shown to be able to suppress the DICE effect and thereby shift the limit of pt-immune BC-P-MOSFETs from 0.6 mu m down to 0.3 mu m. The pt encountered below a channel length of 0.3 mu m has been found to result from a pure DIBL effect rather than an incomplete DICE effect suppression. As a result, a further gain in channel shortening (without pt) would require the channel to be even thinner than 0.04 mu m. >

A simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET. Based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region has been derived. The maximum surface field and the minimum surface potential are used to determine the threshold voltage. The influence of drain voltage on threshold voltage has been included by an equivalent shrinkage of the virtual channel length hereafter called “voltage-length transformation”. This simple but general procedure enables us to account for the drain effect and to extend other threshold voltage models derived under assumption of low drain-source voltage. Predictions for threshold voltage have been compared with results of two-dimensional numerical analysis and experimental data. The comparison has been made for a wide variety of doping profiles, channel length, substrate and drain bias, gate oxide thickness and junction depth. Excellent agreement has been obtained down to submicron channel length.

The punchthrough phenomenon in burried-channel (BC) P-MOSFETs (depletion mode devices) is analysed analytically using the voltage-doping transformation (VOT) technique. The mechanism of punchthrough in a BC-P-MOSFET is shown to be, similarly as in a surface-channel (SC) N-MOSFET, due to the DIBL effect. However in a BC-MOSFET the DIBL effect is shown to be considerably enhanced by the effect of screening of the surface inversion layer of electrons. The new punchthrough current model, an unique up to date, deals correctly with the screening effect and shows high accuracy within a wide range of biases and channel lengths.

In this paper we present a study of the integration of a TOSI gate process on fully-depleted SOI devices by using a CMP-less approach and a detailed electrical characterization of NMOS and PMOS transistors, including transport properties. Tuning of the workfunction has been observed for the NMOS devices by doping the polysilicon before gate silicidation. Functional PMOS and NMOS devices have been tested down to 50nm gate length. PMOS devices exhibits very good Ion/Ioff performances (Ion: 492?A/?m at Ioff: 25nA/?m @ Vdd ?1.2V) despite the relatively thick gate oxide thickness used. The inverters' functionality of the FDSOI SRAM cell with a size of 0.99?m2 has also been demonstrated, reflecting that this technology is a very promising candidate for 45nm LP node and beyond.

In this paper, we present a CMOS NiSi totally silicided (TOSI)-gate on SiON module, based on a single step silicidation of the junctions and the total gate, and demonstrate its industrial feasibility on SRAM demonstrators. The single step silicidation is achieved by the use of an ultra-low initial Si gate electrode and selective S/D epitaxy, which allows us to avoid any additional CMP step. We show excellent transistor morphology, good device results and first functional NiSi TOSI-gate SRAMs in a state-of-the-art industrial cell size indicating the potential of our TOSI integration module for LP applications