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Reinforced isolation provides protection of equipment and operators that interact with high voltage domains. Standards that define it have evolved over time from those that require only partial discharge to confirm reliability at the high voltage operating conditions, to those that also require a time dependent dielectric breakdown model (TDDB) for verifying reliable working voltage. In this paper we assess the impact of AC frequency, waveform, and rise and fall times on lifetime, which are important parameters that are not included in the current standards.

Stacked intermetal dielectrics grown by a Plasma Enhanced Chemical Vapor Deposition (PECVD) technique are widely used as a capacitive voltage divider to integrate low and high power ICs. The voltage-divider must sustain multi-kV operation for years in harsh (hot and humid) environment. Therefore, a fundamental understanding of the degradation mechanisms of the dielectric is an essential prerequisite for its safe operation. While the reliability of PECVD oxides has been extensively studied, the reliability of stacked oxides, with numerous chemically and mechanically polished (CMP) interfaces, is not fully understood. In fact, the dielectric reliability would differ dramatically if the stack behaves as a single thick capacitor vs. if CMP-damaged interfaces render the stack into a set of capacitors connected in series. In this paper, we use a wide range of the stacked intermetal dielectric (= 1∼20 μτη) to study their Time-dependent dielectric breakdown (TDDB) degradation mechanism. Our results demonstrate that the stacked dielectric do behave as a single unit, but unlike conventional TDDB in submicron gate oxide, the TDDB of stacked dielectrics is determined by impact ionization and charge trapping. We explored the degradation mechanism in detail through experiments and simulation; the results are embedded in an acceleration model that can be used to predict TDDB lifetime at arbitrary operating conditions.

In this study, electromigration (EM) reliability of TSV-microbump (μ-bump) joints was investigated. Sn-based μ-bumps with three different schemes of metallization were tested under current stressing at elevated temperatures. EM-stressed μ-bumps, together with thermal anneal-only μ-bumps and as-received controls, were cross-sectioned and characterized using scanning electron microscope (SEM), energy dispersed x-ray (EDX) and focused ion beam (FIB). Intermetallic compound (IMC) growth kinetics under EM for the three types of metallization were obtained, and compared with those subjected to thermal annealing only. Results showed good EM performance of the TSV μ-bump joints, indicating that IMC formation plays an important role in improving the EM reliability of μ-bump joints. However, non-EM related voids were observed in the μ-bumps, and the voiding mechanisms were discussed.

To enable the miniaturization, electrical performance and heterogeneous functionality needs for emerging Analog applications, a stacked Wafer-level Chip Scale Package (WCSP) package platform has been developed using Through-Silicon Via (TSV) technology. This allows stacking of ICs, MEMS, passives and other components in the vertical direction onto active or passive TSV wafers, to create innovative System-in-Package (SiP) product solutions. Since Analog devices are small in size and cost is a key care about, a careful selection of the integration flow is required to achieve a low cost packaging solution. In this work, an integration flow for the stacked WCSP package is presented, along with development details for the Chip-on-Wafer (CoW) bonding and wafer overmolding unit processes. The test vehicle was 3mm × 3mm in size and used 25u diameter Cu TSVs in a 200mm diameter wafer. Interconnect reliability evaluations were done with different micro-bump Under Bump Metallurgy (UBM) and TSV tip surface finish metallization combinations. Wafer ovemolding development included warpage, saw and adhesion evaluations with multiple mold materials. A back-end assembly flow was established with a mass reflow bonding process and an overmold material with low CTE and intermediate T g and modulus. Samples were prepared with mold-on-die and exposed die package structures. Excellent time-zero yields were obtained, with an average TSV micro-bump interconnect resistance of 25 mohms. Results and failures modes from preliminary reliability testing are included.

The formation of hillocks has been studied as a function of process parameter in patterned and unpatterned Al98.5wt. %Si1.0wt. %Cu0.5wt. % films deposited on chemical-vapor-deposited W-coated substrates. The effects of linewidth, substrate temperature during film deposition, and sintering time and temperature on hillock size were investigated. Three types of hillocks are found: the “surface hillocks”, the “side hillock”, and the “line hillock”. These are further classified by their shapes. The surface hillock and side hillock, which have been seen previously, form on patterned metal lines having linewidths greater than the larger Al alloy grain sizes (~3 μm). None is seen on linewidths between 0.9 and 2 μm where long-range grain boundary diffusion cannot occur. A new type of hillock, the line hillock, is seen to occur on metal structures having linewidths of 0.6 μm. The line hillock is inconsistent with the current understanding of hillock formation and may present severe restrictions on the downsizing of ultra-large-scale integrated devices.

The microstructural and morphological properties of thin (6000 Å) Al98.5wt. %Si1.0wt. %Cu0.5wt. % films on chemical-vapor-deposited tungsten-coated substrates have been characterized as functions of substrate temperature during deposition and a postdeposition sinter. Scanning electron and transmission electron microscopic investigations show these properties can be categorized with respect to the substrate temperature during deposition. The Al98.5wt. %Si1.0wt. %Cu0.5wt. % films deposited on substrates heated at temperatures ≤200 °C are rough and are comprised of rounded grains. For deposition on substrates heated at ≤300 °C, the films are smooth. Large voids and small precipitates (presumably Al2Cu) are present in the films deposited at 400 °C. The films retain their as-deposited texture during a 450 °C sinter. Precipitates and evidence of W interactions occur in the sintered films deposited on the lower temperature substrates. In addition, the shapes of thermal hillocks and mesa-like protrusions that form during the sintering process are influenced by the films' as-deposited morphologies.

Historically, back end of line (BEOL) or interconnect resistance and capacitance have been viewed as parasitic components. They have now become key parameters with significant impact on circuit performance and signal integrity. This paper examines the types of BEOL variations and their impact on RC extraction. The importance of modeling systematic effects in RC extraction is discussed. The need for minimizing the computational error in RC extraction before incorporating random process variations is emphasized.

Interconnect parasitics are significant and complex components of circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. In this tutorial, four key aspects of copper/low-k interconnect process are discussed: Non-linear resistance, Selective Process Bias (SPB), dummy (fill) metal and process variations. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors. Techniques used in parasitic extraction to model the copper/low-k effects are discussed in detail. Techniques to measure resistance and capacitance in silicon and correlating them to parasitic extraction tools are presented to demonstrate systematic validation interconnect parasitics.

Interconnect parasitics are dominating circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors. Typically, researchers and designers have been using pre-defined set of structures to validate the accuracy of interconnect models and parasitic extraction tools. Unlike industry benchmarks on circuits such as MCNC benchmarks, no benchmarks exist for interconnect parasitics. This paper discusses the issues in accurate interconnect modeling for 130 nm and below copper/ultra low-k technologies. A set of benchmark structures that could be used to validate accuracy and compare parasitic extraction tools is proposed. Silicon results from 130 nm technology are presented to illustrate the usefulness of these benchmarks. Results of application of these benchmarks to compare parasitic extraction tools are presented to demonstrate systematic validation of resistance and capacitance extraction.

This paper describes a systematic approach to the use of electrical measurements for interconnect modeling and process monitoring. A fast and area efficient technique to measure interconnect capacitance in a scribe line is discussed. The benefits of this technique in monitoring interconnect process, and in fanning out technology to multiple fabs, in monitoring wafer-to-wafer/lot-to-lot variations and in accurate modeling of capacitance are illustrated using the results from 130 nm copper technology.

Stress-induced voiding is observed in Cu-based, deep-submicron, dual-damascene technologies where voids are formed under the via when the via connects to a wide metal lead below it. The voiding results from the supersaturation of vacancies that develops due to grain growth when the Cu is not properly annealed prior to being fully constrained. The driving force for voiding is shown to be stress migration with a maximum in voiding rate observed at /spl sim/190/spl deg/C. A diffusional model is presented which shows that the voiding mechanism is an issue primarily for vias connected to wide Cu leads. A thermomechanical stress exponent of 3.2 and a diffusional activation energy of 0.74 eV were determined for this stress-induced voiding mechanism.

A new regime of hillock growth has been observed in patterned Al98.5 W.%Si1.0 Wt.%-Cuo0.5 wt.% films. The “surface” hillock and “side” hillock, which have been seen previously, form on patterned metal lines having linewidths greater than the larger Al alloy grain sizes (∼3 μm). None is seen on the fabricated lines having linewidths between 0.9 and 2 μm where long-range grain boundary diffusion cannot occur because of its bamboo structure. However, a new type of hillock, the “line hillock”, occurs in structures having linewidths of 0.6 μm. The presence of this last type of hillock is inconsistent with the current understanding of hillock formation and may present severe restrictions on the down-sizing of ultra–large–scale integrated devices.