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In this work, we study the Transient Liquid Phase Bonding (TLPB) for flip chip interconnexion using copper pillar and SnAg solder alloy technologies. Cu and SnAg bumps with a size of 90 × 90 µm2 were deposited using electroplating process with a thickness of 20 µm and 15–30 µm, respectively. Two types of Cu were deposited: with or without additives. Before the TLPB process, soldering experiments with or without pre-reflow were carried out at 250 °C in order to insure a good filling of the joint. Afterwards, isothermal holdings up to 4 h were performed in the temperature range between 250 and 350 °C under air atmosphere. Two main aspects of Cu/SnAg system are studied and analyzed: (i) the evolution of morphology, microstructure, and growth kinetics of intermetallics (IMCs) during the TLPB and especially (ii) the formation and growth of gas bubbles within the liquid solder during TLPB process. Destructive (scanning electron microscopy) and non-destructive (X-ray) characterizations are performed to analyze and understand the evolution of microstructure as well as the formation and evolution of cavities within the joint during the TLPB process. Non-destructive X-ray radiography with 5 µm resolution and 3D X-ray tomography analysis with 0.7 µm resolution were conducted for the same joint at different steps of its evolution between its initial state (just after the soldering process: about 3 min at 250 °C) and 4 h at 250 °C in order to follow “in situ” the evolution of volume defects inside the joint and especially the evolution of gas bubbles within the joints.

The low-k/ultra-low-k (LK/ULK) dielectric materials are incorporated in the 40 nm technology node and beyond to reduce resistance and capacitance (RC) delays and improve chip performances. However, the LK/ULK integrity becomes critical in a flip-chip process because of the LK/ULK materials' higher porosity and fragility in mechanics. In this paper, we proposed a three-dimensional (3D) one-level global/local finite element model to study stresses and fracture behaviors in the chip with ULK dielectrics in the heating flip-chip process using SIMULIA ABAQUS software. The global model includes an effective thin layer that is equivalent to Cu/low-k multilayer interconnections. On the basis of stress analysis, the precracks at different locations of back-end of line (BEOL) were introduced to estimate the values of energy release rate (ERR) along the 3D crack fronts and the possible crack extension was discussed. Furthermore, the ERR affected by the ULK modulus, polyimide thickness and copper pillar diameter was investigated. The analysis reveals that the values of ERR are higher in upper layers of the BEOL and their values at interfaces of Cu/ULK are as much as two times than in ULK. The ERR reaches its maximum value under the edge of copper pillar with higher first principal stresses. The crack propagation becomes critical due to a quickly rising value of ERR when the polyimide (PI) thickness or the diameter of copper pillar is decreased. The study helps to understand the fracture behaviors in BEOL of an advanced chip during a packaging process.

Purpose The purpose of this paper is to present the experimental and simulation studies on the influence of copper pillar bump structure on flip chip packaging during reflow soldering. Design/methodology/approach In this work, solidification/melting modelling and volume of fluid modelling were used. Reflow soldering process of Cu pillar type FC was modelled using computational fluid dynamic software (FLUENT). The experimental results have been validated with the simulation results to prove the accuracy of the numerical method. Findings The findings of this study reveal that solder volume is the most important element influencing reflow soldering. The solder cap volume reduces as the Cu pillar bump diameter lowers, making the reflow process more difficult to establish a good solder union, as less solder is allowed to flow. Last but not least, the solder cap height for the reflow process must be optimized to enable proper solder joint formation. Practical implications This study provides a basis and insights into the impact of copper pillar bump structure on flip chip packaging during reflow soldering that will be advancing the future design of 3D stack package. This study also provides a superior visualization and knowledge of the melting and solidification phenomenon during the reflow soldering process. Originality/value The computational fluid dynamics analysis of copper pillar bump structure on flip chip packaging during reflow soldering is scant. To the authors’ best knowledge, no research has been concentrated on copper pillar bump size configurations in a thorough manner. Without the in-depth study, copper pillar bump size might have the impact of copper pillar bump structure on flip chip packaging during reflow soldering. Five design of parameter of flip chip IC package model was proposed for the investigation of copper pillar bump structure on flip chip packaging during reflow soldering.

Thermal compression bonding (TCB) has been widely used in flip chip bonding processes for three-dimensional integrated packaging. Therefore, studying the TCB process and solder joint structure is significant for improving reliability. In this study, a Ni layer was deposited between the Cu/Sn-3.5Ag solder bumps of upper and lower chips, and TCB process tests were carried out at different bonding temperatures, forces and times. The solder height at the top and bottom of the copper pillar were recorded. Through the establishment of a mathematical analysis model, the relationship between the solder joint height and maximum stress was analyzed theoretically, and the trend of the shear stress and solder joint height was obtained from die shear tests. Then, the solder joint morphology, strength and microstructure composition of the microbumps were observed after aging. Our results showed that the growth rate of intermetallic compounds (IMCs) for Cu/Sn-3.5Ag microbumps with a 25 μm diameter was 2.5 times those with a 100 μm diameter and that the Ni barrier layer prevented the diffusion of Cu in Sn-3.5Ag solder. In addition, the Ni layer improved the strength of the Cu/Sn-3.5Ag joints after aging. Finally, with extended aging time, the fracture site was found to move from the solder region to the Cu6Sn5 layer for the Cu/Sn-3.5Ag samples, while it remained at the Sn-3.5Ag/IMC interface for the Cu/Ni/Sn-3.5Ag samples.

Open-cell metal foams suffer from severe deterioration in mechanical properties due to their enriched three-dimensional interconnected holes. In this paper, reinforcing copper pillar(s) or tube(s) are embedded into the foam matrix to form “composite” structure to enhance the open-cell copper foams. To do this, a simple positioning device is designed for preparation of the green porous copper aligned with directional through hole(s) based on a tapping method. Then the reinforcing pillar(s) or tube(s) are inserted into the hole(s) and sintered together. By this means, the mechanical properties of the copper foams are significantly improved. The energy absorption capacity of the composite foams has also been improved because of a higher and wider yield platform compared with the unreinforced copper foams.

Microacoustic radio frequency filters are essential electronic components for all devices using wireless communication. For miniaturization and cost reduction it is necessary to further reduce the area for the electrical contacts on the chip. CPB (copper pillar bump) interconnections on radio frequency filters can release valuable chip design area of up to 26 % compared to standard SB (solder bump) interconnections on a Qualcomm TFAP (Thin Film Acoustic Package). We developed a process to deposit CPB interconnections on microacoustic radio frequency filters. A 1.20 mm $\times1.60$ mm SAW (surface acoustic wave) LTE (Long Term Evolution) band 26 duplexer with a height of 0.20 mm including the CPB interconnections was investigated. Unbiased highly accelerated stress test, damp heat steady state, dry heat, and temperature cycling reliability tests have shown that the new interconnection technology fulfills the reliability requirements of the smart device industry. Two failure modes caused by extended temperature cycling were identified via scanning acoustic microscopy and scanning electron microscopy analyses on cross sections.

Cu plating bath for high-speed electrodeposition of Cu pillar was designed in consideration of a flat top morphology of pillar and a pillar height uniformity. An ideal polarization curve was assumed for the flat top morphology. To obtain the ideal polarization curve, an effect of organic additive concentration and solution agitation on the polarization curve were investigated. The basic bath components were optimized considering a Wagner number to improve the pillar height uniformity. To confirm the pillar top morphology and the pillar height uniformity, a 300-mm diameter wafer was plated with Cu at 20 A/dm2. As a result, improved pillar top morphology and pillar height uniformity were obtained. The optimized plating bath was applied to the plating of a large-size panel of 415 × 510 mm.

The finite element software ANSYS was used to simulate the solder joints in the flip chip, and the stress and strain distribution results of the solder joints are displayed. During the simulation process, the final results of the simulation were not the same when the solder joints of different sizes were used. The simulation results under thermal cycling load show that the area where the maximum stress and strain occur is mostly distributed in the contact area between the solder joint and the copper pillar and at the solder joint. During the entire thermal cycling load process, the area where the maximum change in stress and strain occurs is always at the solder joint, and when the temperature changes, the temperature at the solder joint changes significantly. From the comprehensive analysis, the relevant empirical correction calculation equation is used to calculate and predict the thermal fatigue life of the solder joint. We found that when the diameter of the solder joint is constant, the increase in the height of the weld point will increase its thermal fatigue life; when the height of the weld point is constant, the increase in the diameter of the weld point increases its thermal fatigue life. The effect of height is greater than the effect of diameter.

Low-thermal-budget (180 °C for 15 sec) Cu pillar to Cu pillar bonding with Pd passivation under the atmosphere is developed without any planarization pretreatment before the bonding process. The bonded structure is investigated with material analysis, electrical measurement and reliability test. The results show that although the Cu pillar has a high roughness surface due to the electroplating process with a high deposition rate, Cu atoms can still diffuse and connect through the passivation layer and perform the low-thermal-budget Cu pillar direct bonding. Low specific contact resistance and stable resistance of daisy chain shown in the reliability test reveal the excellent bonding quality and integrity. This Cu-Cu bonding method is therefore favorable for chip stacking technology development in 3D packaging domain.

Due to the existence of anisotropy, the previous isotropic assumption of silicon-based materials can no longer accurately characterize the mechanical behavior of materials. In this study, finite element analysis (FE A) method was adopted to research the effect of silicon anisotropy on the thermal stress of through silicon via (TSV) structure including copper pillar arrays in stacked 3D packaging chips under thermal cyclic loads. The simulation results show that, in both isotropic and anisotropic cases, the high thermal stress is always located at the interface between two materials in the structure. Compared to the isotropic case, the magnitude of thermal stress is always larger in the anisotropic case. In both isotropic and anisotropic cases, the maximum thermal stress in the bottom TSV copper column arrays is always slightly larger than that in the upper layer arrays, and the thermal stress of the copper column at the farthest diagonal line is most concentrated.

The continuous demand for high-speed, low-power consumption and multi-functionality of new generation electronic products has led to an exponential increase for high-yield and high-reliability packaging technologies, which has promoted the application of the 7nm node process technology to promote higher I/Os and smaller bump pitches. The advantages of copper pillar bump, which was widely used in high-density packaging, include fine pitch, high strength, low interconnection resistance, excellent electromigration performance, and lead-free packaging solutions. The low-k/ultra-low-k (LK/ULK) material medium used in back-end of the line (BEOL) can effectively reduce the parasitic capacitance without reducing the wiring density. Therefore, to improve thermomechanical and electrical performance, chips with a 42nm node and beyond usually integrate LK/ULK structure and metal line in BEOL. However, the encapsulation of the chip exceeding the 28nm node would lead to a sharp increment in the number of BEOL interconnection layers (vertical) and high-density copper traces (horizontal). The thermomechanical stress caused by the mismatch of the CTE of wafer and packaging material may cause LK/ULK delamination, bump cracks, and UBM peeling failures. Therefore, the accurate analysis and calculation of the thermomechanical stress in the film structure has always been the focus of engineering and academia. The integrity of the bumps and microstructure of BEOL can be evaluated effectively by shear test method, which was suitable for structural inspection. In this work, the shear test simulation was applied for single bump to characterize the failures of BEOL structures, e.g., fractures of ULK/LK. Owing to the fragile characteristics of LK/ULK, BEOL was susceptible to external loads. When the copper pillar bumps above BEOL were subjected to shearing forces caused by thermal mismatch, the failure would occur in some microstructures within BEOL, especially in ULK/LK interfaces. Because the bumps near die corner suffered a critical shear load, so the single bump of the aforementioned area was investigated by a shear simulation model. Studies had shown that the shear rate had less effect on the maximum shear stress, but the increment of the shear height brought about more fractures of LK, which showed that reducing the bump height helps to reduce the risk of BEOL damage under thermomechanical loads. Generally, the shear test of copper pillar bumps could effectively evaluate the strength and adhesion of the BEOL film interfaces. As an early evaluation under extreme conditions, this simulation was designed to check the integrity of ULK/LK stack film and the strength of the bump structure through the chip package interaction without underfill protection and finally find the optimal packaging solution.

As the distance between the copper pillars and the size of the solder continues to shrink, the solder joints are subjected to extremely high current density and thermal energy density. This paper is aiming to analyze the electromigration reliability of solder joint with different shapes. Both experiment and finite element method (FEM) analysis were performed to investigate the Mean-time-to-failure(MTTF) of solder joints. Firstly, finite element models of solder joints were established. And then, the current density, temperature, and stress distribution in the solder joints were analyzed according to the model. After that, the chip samples were made by thermal compression bonding. The electromigration experiments were carried out at 150°C, and the interface evolution of solder joints with different shapes was analyzed. Finally, the modified Black's formula was adopted to calculate the MTTF of three different solder joints. According to the calculation results, it can be obtained that cylinder-shaped solder joints have better electromigration reliability than hourglass-shaped bumps and barrel-shaped bumps.

Copper is the most common interconnected materials in the field of microelectronic packaging, and it is widely used in various advanced package technologies, such as redistribution layer (RDL), copper pillar (CuP) and under bump metallization (UBM) etc. However, the rapid development of packaging technology, decreasing size and increasing Joule heat make a great challenge on the mechanical properties and thermal stability of copper interconnected materials. It was widely reported that the nanotwinned copper had very high strength and excellent conductivity, which was quite suitable for the next generation interconnected materials. However, different from electroplating thin films, the achievement of uniformity and flatness for electroplating ultra-fine pitch nanotwinned RDLs would be difficult since the line width was as low as 1.5µm. Through the study of growth mechanism and additives effect, we had invented an acid nanotwinned copper electrolyte as reported previously. So in our study, the evaluation of modified nanotwinned copper electrolyte was conducted in order to clarify its performance of on the electroplating ultra-fine pitch RDLs. Also, three kinds of commercial RDL electrolytes were served as comparisons. In detail, different electrolytes were evaluated from the aspect of microstructure, hardness, thermal stability, uniformity and flatness. Firstly, the morphology of electroplating copper film was characterized by focus ion beam (FIB), and then the hardness was measured. The thermal stability was revealed by the hardness evolution before and after heat treatment test. Finally, the 1.5µm, 4pm and 1.5µm RDLs were electroplated on a patterned wafer, and their uniformity and flatness were calculated. Both uniformity and flatness showed a decreasing tendency basically when the line width kept decreasing. The uniformity and flatness were 6.73~13.89% and 2.32~4.17% respectively for nanotwinned copper electrolyte, which was at the upper level compared to the commercial RDL electrolytes.

Delamination between the underfill and the copper pillar or copper solder pad is one of the major drawbacks of microelectronic packaging, leading to premature failure of the entire device. In this study, the chemical oxidation method was used to improve the adhesive strength between copper and underfill. It was found that the adhesive strength of copper and the underfill was significant increased by oxidation treatment of the copper. The wettability of the copper substrates was improved by the three oxidants (Na 2 S 2 O 8 , CuCl 2 , and KMnO 4 ) and was reduced by the oxidant of H 2 O 2 . SEM characterization results showed that different microstructures were formed on the oxidized copper surface. Through the analysis of the results of XPS, the surface layer of the oxidized copper changed from Cu metal layer to CuO layer. These results indicated that the wettability, microstructure, and oxide layer affected the adhesive strength of the copper/underfill interface.

3D packaging is able to keep the scaling in semiconductor market. Increased and shorter interconnects achieved by vertical stacking have benefits such as improved performance, reduced signal delay, and small form factor. In order to obtain high-quality 3D packaging applications, the integration of heterogeneous devices through bonding technologies is very important. Low temperature and pressure are essential during the bonding process because most of logic/memory devices has many metal and low-k dielectric layers, which are vulnerable to thermal budget and mechanical stress. Therefore, a small amount of solder with a low melting point is presently used on the top of the copper pillar for mass production. But, solder creates an intermetallic compound with copper at the bonding interface and cannot be applied to fine pitch patterns due to their reflow characteristics. Thus, Cu is emerged as a promising interconnect, but Cu-Cu bonding has few challenges because copper is easily oxidized and has a high melting point. In this paper, copper nitride, which prevents oxidation of the copper surface and promotes low temperature bonding, was studied by two step Ar/N 2 plasma treatment. The optimum thickness of copper nitride passivation was derived using the design of experiment. It was also found that the copper nitride layer was almost decomposed at a temperature of 200°C.

In previous works, the resulting damages in the back end of line (BEoL) stack triggered by Copper pillar (Cu-pillar) shear-off events were evaluated and classified [1]. It was determined, especially by utilizing acoustic emission (AE) measurements, that damage events consist of multiple extremely fast sub-processes. The objective of this work is the development of an approach to enable the identification of the areas of damage initiation and comprehend the damage propagation in a BEoL stack under mechanical load by triggering only the initial sub-processes. Mechanical stress was induced into the BEoL stack utilizing a displacement-controlled sub-critical Cu-pillar loading approach with the approximate parametrization determined in previous experiments [1]. During mechanical loading, AE signals were constantly measured. As soon as significant acoustic events were detected, the experiment was aborted. The occurring damages were analyzed utilizing a customized nano X-ray computed tomography (nXCT) setup and focused ion beam (FIB) milling as well as scanning electron microscopy (SEM) imaging. In this work, a methodology could be developed to enable the evaluation of BEoL damages in an early, sub-critical stage. These results provide a better understanding of the damage formation and propagation in the BEoL stack and enable a design optimization procedure for the most damage prone areas.

Flip-chip interconnects made entirely from copper are promising candidates to overcome the intrinsic limits of solder-based interconnects and match the demand for increased current densities of high-performance microprocessors. To this end, dip-based all-copper interconnects have been demonstrated to be a viable approach to form electrical interconnects by sintering copper nanoparticles between the copper pillar and pad. However, the performance of this technology is limited by residual porosity of the copper joint formed between the pillar and the pad during sintering. Moreover, the applicability of this technology in the printed circuit board industry is constrained by thermomechanical stresses that arise from the sintering. Furthermore, the compatibility of the sintering approach with standard finishing layers used as diffusion-barrier layers to provide wetting and to prevent the oxidation of the pillar and pad surfaces is unknown. In this paper, we pursue the advancement of dip-based all-copper interconnect technology. We demonstrate the robustness of dip-transfer of copper paste for varying withdrawal velocities and typical nonuniformities in copper pillar heights. Moreover, we prove the applicability of this technology with fine pillar diameters and pitches down to 10 and $20~\mu \text{m}$ , respectively. In addition, we demonstrate reduced porosities of the copper joints by applying pressure during the bonding process at 200 °C. This densification leads to interconnects with four times the shear strength and half the electrical resistance compared to interconnects formed without the application of pressure. In addition, the bonding temperature is decreased to 160 °C by applying a novel copper paste formulation, reducing the thermomechanical stress in the assembly caused by the cooling from the sintering temperature. Finally, the compatibility of this technology with EPAG, ENIG, and ENEPIG finishing layers is demonstrated, with resulting shear strength of the interconnects above 70 MPa and electrical resistance comparable to the unfinished samples.

A new kind of intermetallic compounds (IMC) were found around copper pillar in micron level bumps. To investigate the formation mechanism, three different sized Sn/Ni/Cu bumps (10 μm, 20 μm, 50 μm) were electroplated then reflowed at 230 °C for 100 s. After reflow process, a thin layer of IMC was formed around copper pillar, which is attributed to surface wetting behavior. After aging at 170 °C and 200 °C for different times, the growth mechanism of sidewall IMC was observed by scanning electron microscopy combined with electron backscatter diffraction (EBSD) technology. Surface diffusion was considered to be the main driving force for sidewall IMC growth for the activation energy of them was found to be much smaller than that in previous studies. The EBSD results showed a preferred orientation of sidewall Cu3Sn grains being perpendicular to copper periphery, which indicated direction of Cu atoms flux during Cu3Sn growth. Formation mechanism of this novel sidewall IMC was proposed based on surface wetting and surface diffusion. The findings contribute to the failure mechanism study in small size bumps and provide insights into the reliability of 3D electronic packaging.

The local stress distribution in a silicon chip encapsulated in an area-arrayed copper pillar-type flip-chip package was evaluated using specially designed test chips. Stress is sensed using piezoelectric resistors, which are p-type and n-type diffusion resistors embedded in a silicon chip measuring 7.8 mm $\times7.8$ mm. Each piezoelectric resistor measures approximately 0.03 mm in length and 0.002 mm in width, which is sufficiently small to measure the local stress distribution near each copper pillar. As a result of this study, it is revealed that the copper pillars have an impact on the local stress distribution in silicon chips, in particular producing a large stress gradient near the copper pillar edge, compared to the conventional wire-bonded packages. Since large stress gradients disturb pair characteristics of analog circuits, in order to design a high-precision integrated circuit employing a copper pillar-type flip-chip package, a specific regulation method to avoid overlap with the copper pillars is needed to maintain the accuracy of the analog circuits.

The demand for high-performance, high-functionality packages for integrated circuits continues to grow. Three-dimensional (3D) integration is strongly being pursued to meet this demand and has started to reach maturity and industrial adoption. As advanced 3D system designs progress, requiring higher 3D interconnect density with pitches of 10 μm and lower, traditional chip attachment through solder bump technology will likely face complex manufacturing and reliability challenges. Cu-Cu thermocompression bonding has been proposed as a key 3D-enabling technology and alternative to solder. One of the main issues challenging its commercialization in high-volume manufacturing is the sensitivity of Cu-Cu bond quality to prebond surface conditions. This is especially true for die bonding applications which have limited rework options once chips have been singulated. This article outlines further development and demonstration of a tack and collective bonding scheme for Cu-Cu thermocompression bonding. This approach mitigates many of the thermal and throughput issues of a chip-level Cu-Cu attachment process by performing the quick chip alignment at a low temperature and then subsequently completing all Cu bonding simultaneously. The specific use of an intermediate handle wafer between the tack and collective bonding steps allows chips to be reconstructed into a wafer form that facilitates the cleaning and surface preparation of the chips before bonding using standard wafer processing equipment. A chip-to-wafer test structure designed for Cu pillar-to-pad bonding was used as part of this demonstration and illustrates the feasibility of the application. Full transfer of chips to a receiving device wafer using the tack and collective bonding process is shown with electrical test results and selected bond-integrity metrology confirming substantial bond yield and strength.

Temperature cycling has been used as a reliability test for electronic products. Due to large thermal mismatch between silicon chip and substrate, stress is developed at the bump interconnection during temperature cycling. Multiple bump failure modes have been observed during temperature cycling tests, such as aluminum pad (AP) crack, polyimide (PI) crack and delamination, silicon passivation crack and delamination, AP/under bump metallization (UBM) interfacial delamination, etc. It is important to understand the failure mechanisms underlying these failure modes. In this study, finite element models have been developed to understand the potential failure mechanisms of these failure modes. It is shown that the failure modes are related to aluminum plasticity. A mechanistic model is proposed in this study to expose the impact of aluminum plasticity on the stress increase in the overlaying layers on the aluminum pad. It demonstrates that the stress increase within the overlaying layer, such as silicon passivation, was caused due to plasticity of aluminum pad. Thus, the plasticity effect of aluminum pad must be considered to capture the failure mode related to the overlaying layers. A three-dimensional model was further developed to evaluate the failure metrics associated to different failure modes. Simulation analysis also evaluates the impact of copper pillar height, AP size, and PI opening (PIO) on these failure modes. The results help to optimize design factors to mitigate the bump failure risk.

To keep up with the demands for smaller antennas with increased performance and decreased costs, most next generation architectures mandate higher IC (integrated circuit) chip integration. Compared to conventional packaging configurations, advanced chip packaging technologies, such as 2.5D and 3D, offer greater chip compatibility and lower power consumption. Given these advantages, the adoption of advanced packaging is inevitable. Within advanced packaging, the copper pillar interconnect is a key enabling technology, and the next logical step. This technology offers several benefits, including improved electromigration resistance, improved electrical and thermal conductivity, simplified underbump metallization (UBM), and higher I/O (input/output) density. The fine pitches that copper pillars allow helps the technology to supersede solder bump technology, which reaches its lowest pitch around 40 microns. Finer pitches allow for a higher I/O count, which increases performance. In this work, assembly of ultra-thin MMIC (monolithic microwave integrated circuit) GaN (gallium nitride) fine-pitch copper pillar flip chip assemblies on high density interposers was successfully demonstrated. Using pitch copper pillar flip chip, the assembly processes for both organic PCB (printed circuit board) and silicon interposers were evaluated, both with an ENIG (electroless nickel gold) pad finish. For the 2D/2.5D/3D assembly process development, a standard in-house pick and place tool was used, followed by mass solder reflow, finished with an underfill for reliability test. The interconnect robustness was determined by die pull strengths and cross-sections. Complete reliability and qualification test data on GaN copper pillar flip chip 2D assembly was completed, including 700 temperature cycles and UHAST (unbiased highly accelerated temperature/humidity stress test).

Current electronic devices and features sizes are becoming smaller, lighter, with ever-increasing electrical performance requirements. For flip chip devices, Cu-pillar technology enables reduced pitch and reduced package size with good electrical performance. Cu-pillar interconnects require the development of reliable interconnects including many design features such as: die thickness, underfill materials, and substrate design. The enhanced design is needed to avoid issues associated with package warpage, die backside stress, low-k dielectric cracking (during chip attach and temperature cycling), solder joint reliability, and electromigration failure. This paper presents mechanical simulation through finite element modeling of Cu-pillar interconnects and package designs to help the design selection process to improve the reliability of the package under thermal-mechanical loading conditions. The simulation uses a technique of homogenized properties of the Cu-pillar and the underfill material in the die-attach area in the global model to determine stresses. Two failure modes were assessed: a) Brittle fracture of the die and b) Interface delamination between Al pad/die interface. Results show that a thinner Si die has a lower risk of brittle crack compared to the thicker die of 300um. The use of mold compound with higher coefficient of thermal expansion (CTE) reduces delamination risk of the Al pad.

A novel approach is presented to evaluate the mechanical stability of back end of line (BEoL) stacks. A SRAM test vehicle manufactured in 28 nm technology with copper pillar bumps is used. In a second step, the validity of the approach is also shown for a second sample manufactured in 22 nm technology and the experimental results are compared. To inflict damage to the BEoL stack of the respective semiconductor device, external forces are applied to the copper pillars (Cu-pillars) by shear loading using a tribo-indenter system. An acoustic emission (AE) detection sensor is attached to the sample to measure acoustic waves during the shear experiment as an indication for damage. The damage progression in the BEoL stack is extremely fast, hence details can't be resolved anymore with the piezo sensors of the tribo-indenter. However, due to the much higher temporal resolution, AE measurements give a more precise insight into the damage process. The resulting damages are imaged using nano X-ray computed tomography (nXCT) as well as scanning electron microscopy (SEM). The results provide a better understanding of the origin and the propagation of damages in the BEoL stack.

Failure analysis is crucial in improving semiconductor manufacturing yields. Yield improvement is done by collecting, analyzing, identifying the causes of defects, and applying corrective actions to resolve the root causes. With the ongoing miniaturization of TSVs, micro-bumps, RDLs, and other package interconnects [1], detecting defects in these buried interconnects is becoming more difficult as well as more important. Traditionally semiconductor packages are cross-sectioned to identify internal process defects such as unsolders, solder shorts, and pad misalignment. Cross-sectioning is a destructive approach, is difficult to do, and provides information in a single 2D plane only. Due to the large effort and the destructive nature of this approach, the amount of data that can be generated is typically quite limited. The development of 3D x-ray microscopy provides industry with the capability to image and analyze buried features such as micro-bumps, TSVs, and other metallic structures using a non-destructive, 3-dimensional technology [2]. At the same time, deep learning has revolutionized other technologies such as visual surveillance, predictive maintenance [3], object detection [4], and is now revolutionizing defect detection in semiconductors. When used together, the combination of 3D x-ray microscopy and deep learning is establishing a new paradigm in package inspection and metrology. In this paper, we will present a novel method for automatically detecting internal anomalies in semiconductor packages and using deep learning to assess the attributes of these interconnects. Chips representative of stacked 2.5D packages were fabricated and assembled using thermo-compression bonding. Bonding parameters were varied in order to create packages with different bond line thickness, different solder fillet shapes, and various pad alignment scenarios. A commercial 3D x-ray imaging tool was used to create high-quality tomographies of these packages. Deep-learning and computer vision-based methods were employed to automatically detect internal features and measure attributes. A three-step procedure was used for data analysis. In the first step, a bounding box was detected for each region of interest (Copper Pillar, Pad, etc.) using a modified single shot detector object model. In the second step, we isolated features within the region of interest and performed 3D segmentation on them. The third and final step utilized automated 3D metrology using the segmented regions. Robust 3D computer vision techniques were deployed to measure the extent of voids which are key attributes for the chip fabrication and process control step. This is the first part of a multi-part paper.

Replacing solder ball interconnects through copper pillar bump (CPB) interconnects on acoustic wave components (AWC) like SAW (surface acoustic wave) filters saves valuable chip space and facilitates chip miniaturization. In this contribution, we present our very first assembly and reliability results for CPBs on lithium niobate chips with TFAP(tm) (Thin Film Acoustic Package) for SAW filters. The CPBs consist of a Cu/Ni/SnAg layer stack and are soldered on a test board with Cu/Ni/Au finish. Leaving aside premature failures due to poor soldering, CPBs withstand 770 cycles of RCoT (Rapid Change of Temperatur, −40°C / + 125°C) reliability testing. The solder joints were investigated via cross section micrographs. Additionally, uHAST (Accelerated Moisture Resistance - unbiased HAST), DH (Dry Heat) and DHSS (Damp Heat Steady State) reliability tests were performed.

In this paper, TGPs with thickness of around 0.53 ∼ 0.6 mm are developed with copper plate as the casing material, nanostructured copper foam as the wick and electroplated copper pillar as the support of vapor core. The effects of charge amount of water, nanostructured wick, the number of copper foam layers and vapor core thickness on the thermal performance of the developed TGP are experimentally studied. It is found that increasing the number of copper foam layers or vapor core thickness can greatly lower the TGP thermal resistance. Specifically, a TGP with a double layers copper foam wick has a much better thermal performance than that with single layer even though the total wick thickness and porosity remain unchanged. Experimental results also show that the multiscale micro/nanostructured wick is beneficial for improving the TGP thermal performance. Small change of vapor core thickness can lead to great change of TGP thermal performance. The ultrathin TGP can reach an effective thermal conductivity of 2207 W/(m·K) at an input power of 22.66 W over a heating area of 8 mm × 8 mm.

SAW-filters (Surface Acoustic Wave) are used for mobile data transfer. Further miniaturization was achieved by replacing the standard interconnect technology via solder balls through CPBs (Copper Pillar Bumps) using a thick film photolithography. CPBs on SAW-filters with a height of approximately 80 μm after reflow, a diameter of 67 μm, almost vertical sidewalls, and excellent adhesion to the seedlayer were fabricated.This study describes in detail the spin coat recipe and the impact of lithography parameters. CPBs were structured with a positive tone photoresist, with a thickness of at least 80 μm (including pre-wet) and almost vertical sidewall resist opening shapes on TFAP™ (Thin Film Acoustic Packaging) packages. The sidewall shape of the resist openings strongly depends on the softbake duration. Exposure dose and post exposure bake duration do influence the resist opening diameters but not the resist sidewall shape if softbake duration is set correctly. The development process had no significant influence.Different tools and processes for plasma cleaning after resist development were investigated to optimize the adhesion of electroplated CPBs. A plasma tool with backside cooling and electrostatic chucking of the lithium niobate wafers allowed an appropriate plasma cleaning descum. The adhesion was determined via shear testing of copper pillars and a subsequent failure mode analysis with optical microscopy.The positive tone resist does not show any damage or peeling from the substrate after the optimized plasma cleaning process or after electroplating of copper, nickel and tin silver alloy. The CPBs withstand all further process steps including DBG (Dicing Before Grinding).

The continuous evolution of electronic devices has increased a serious concern on 2.5D and 3D advanced packaging. Applications in domains such as displays, automotive, defense or space, require large volumes of interconnects to cover large areas in order to achieve better performances for monolithic components. One of the main challenges of large surface interconnects for display applications, is the assembly control with a yield close to 100 % on the entire device surface.This must be guaranteed whatever the components shape, their positive or negative bow and warp or its interconnection pitch. The flip-chip based attachment technology using copper (Cu) pillars with tin solder family capping has become the mainstream process choice for fine pitch configurations. Moreover, the industrial supply chain for such kind of interconnections is today available in the packaging industry, however at much higher pitch than that we develop in Research and development level. With the increase of the die dimensions and the decrease of the pitch and bump diameters (higher resolution demand of the market), the associated number of interconnects per device is also increasing. Therefore, the manufacturing challenges in terms of bump height, Cu pillars field, bow and warp variations for such big dies, and the tin oxide issue management, have become extremely stringent. If the pillars are too short, too tall, have large height distribution, or inhomogeneous solder thickness to match the cumulated warpage of the assembly, we will have to face serious hybridization issues. Indeed, the solder during the reflow process will not wet properly the opposite pads or will flow over the copper pillar sides leading to electrical open or short failures. This finally will lead to a poor hybridization yield.The heterogeneity of the stacked materials used to build the active devices (Top dies with polymers, oxides, metals, semiconductors) highly complicates the control of the components behavior at the hybridization temperatures needed by the lead free solders. The same happens when increasing the interconnection area. Indeed, with high bow due to the internal mechanical stress induced by the heterogeneous nature of the components stack, and its resulting shape (concave or convex, or warped); the connections may be only effective at the borders of the sample. As the die attach pattern density becomes complex, sparse on a part of the surface (typically at the edge) and very dense on the other parts (typically in the center), assembly parameters due to such configuration of the devices becomes a big packaging challenge. In this paper, we present hybridizations with high wettability yield of surfaces around 4 cm2, Cu pillars-based on Silicon substrates with 500000 interconnects and compatible with high quality polymer underfilling without voids. The influence of different bow values, assembly parameters and techniques have also been investigated. A particular focus will be made on the extent of the characterizations. These promising results authorize the possibility to extend applications of Cu pillars to higher interconnect areas on monolithic devices with lower pitches.

Multichip stacking technique is becoming more and more essential for the development of advanced 3D heterogeneous systems with TSVs in the era of AI and 5G. Motivated by the desire to realize such future system integrations, we have developed an advanced multichip stacking prototype module which contains four dies stacking on an interposer with fine pitch copper pillar micro-bumps and TSVs. The minimum diameter and pitch of the micro-bumps employed was with 18μm and 30μm, respectively. While, the diameter and pitch of the TSVs employed was with 10μm and 100μm, respectively. The DC resistance of a long serial signal chain which transfers from the organic substrate to Die_3, then to Die_2, then to silicon interposer, then to Die1_1, then to Die1_2, and finally back to the organic substrate, was measured in the rage of 6~9Ω, indicating a good stacking uniformity. The proposed multichip stacking technique is expected to be applied to the development of future 3D heterogeneous integration applications.

In 3D electronic packaging, microbumps show great potential for vertical connection of stacked chips. The diameter of microbumps, which determines the surface/volume ratio, has great influence on the generation of Intermetallic Compounds (IMCs). To study the intermetallic reaction within different diameter microbumps during aging process, the 20 μm, 10 μm and 7 μm diameter Cu/Ni/Sn copper pillar bumps were prepared and reflowed. After aging treatment, the cross-section of microbumps was observed and analyzed. We observed sidewall Cu 3 Sn around Cu pillar. Cu pillar was eroded into a cone in 10 μm and 7 μm diameter microbumps after aging treatment. We also found that the growth rate of sidewall Cu 3 Sn increased with the microbumps diameter decreasing.

A novel approach is presented to evaluate the mechanical stability of back end of line (BEoL) stacks. A SRAM test vehicle manufactured in 28 nm technology with copper pillar bumps is used. To inflict damage to the BEoL of the given semiconductor device, external forces are applied to the copper pillars by shear loading using a tribo-indenter system. An acoustic emission (AE) detection sensor is attached to the sample to measure acoustic waves during the shear experiment as an indication for damage. The damage progression in the BEoL stack is extremely fast, hence details can't be resolved with the piezo sensors of the tribo-indenter anymore. However, due to the much higher temporal resolution AE measurements give a more precise insight into the damage process. The resulting damages are imaged using nano X-ray computed tomography (nXCT) as well as scanning electron microscopy (SEM). The results provide a better understanding of the origin and the propagation of damages in the BEoL stack.

With the increasing requirement for advanced technology nodes in high-performance devices, low-K (LK), ultralow-K (ULK) and extreme low K (ELK) dielectric materials have been integrated with copper pillar bumps in Back-End-of-Line (BEOL) interconnects in flip chips to reduce capacitance and thus resistance-capacitance (RC) delay. The dielectric materials (LK, ULK and ELK) are fragile compared to silicon oxide. Due to large coefficient of thermal expansion (CTE) mismatch between the die and substrate, dielectric crack and delamination can be induced by the stress transferred by the stiffer copper pillar bumps during chip attach reflow. It is thus important to characterize silicon BEOL strength for chip-package-interaction (CPI) qualification.Bump shear provides a quick method to characterize the silicon BEOL strength by shearing the copper pillar bumps. However, the failure mode in bump shear test is complex and poses a challenge for understanding the failure mechanism. It was observed experimentally that the failure mode induced by bump shear depends on the shear height. Generally, brittle dielectric failure can be induced with a higher shear height. In contrast, ductile Aluminum pad (AP) failure can occur with a lower shear height. A mixed failure mode of both dielectric failure and AP failure may also occur, making the failure mechanism more complex. Furthermore, it was found that metal layout in the BEOL could also affect the critical shear force in the shear load curve.This paper presents a numerical model for better understanding the failure mechanism of BEOL in bump shear. First, a stress model is developed to understand the stress distribution in bump shear. In this work, a contact/target element model is used to simulate the interaction of shear tool surface with the bump surface and a cohesive zone material (CZM) model is used to simulate the potential interface debonding. Plasticity of copper pillar is also considered to capture the plastic energy dissipation. Therefore, the bump/shear tool interaction, energy release due to crack propagation and copper plastic energy dissipation can be well captured in the model. Then an ELK fracture model is also developed to understand the BEOL crack failure. The impact of metal density on ELK crack is evaluated by comparing the energy release rate at the crack tip. The impact of dielectric material properties on the ELK crack is also evaluated. The numerical models provide a good understanding of the stress distribution and BEOL fracture mechanism in bump shear.

Mechanical integrity of low-k dielectrics continues to be an important focus for advanced semiconductor devices. In wafer fabs, while great efforts are made to control individual processing steps, in some cases the overall mechanical quality of the finished silicon dies is not effectively monitored. As a result, defects such as cohesive fracture or interfacial delamination may only manifest themselves during component backend assembly, system board manufacturing and/or field deployment, bringing significant potential disruption and impact to production, product quality, and delivery fulfillment. As silicon and package sizes continue to grow, chip-packaging interaction becomes more significant and the effects of low-k defects also grow as a result. Therefore, it would be of great value to have a quantitative understanding of low-k integrity quality as early as possible, ideally at the wafer or bare die level. The adoption of Cu pillars on fine-pitch flip chips has provided an opportunity for such a purpose. Mechanical tests such as shear testing on individual Cu pillars can be performed, and the response data can be an indicator of the integration quality of the low-k stack. In this study we present results of Cu pillar shear testing on both known-bad and known-good wafer lots of the same device. Response data including load-distance curves and ultimate fracture strength are analyzed and presented. In addition, finite element models have been developed to simulate the test structure and shear testing process. Effects of multiple contributing factors to the shear testing response are evaluated and the results are compared with real shear testing results.

This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field-programmable gate array (3D-AFPGA) design based on an extension of pre-existing two-dimensional-field-programmable gate array (2D-FPGA) tile designs. The periodic nature of FPGAs permits the use of an alternative approach, whereby the design entails splitting the FPGA design along tile borders and inserting through silicon vias (TSVs) at regular spatial intervals. This serves to enable true 3D performance (i.e., full 3D signal routing) while leaving most of the 2D circuit layouts intact. 3D signal buffers are inserted to handle communication between vertical and adjacent neighbors. For this approach, the density of vertical interconnections was shown to be determined by the size of the bond pads used for tier–tier communications and bonding. As a consequence, reducing bond pad dimensions from 25 μm to 15 μm, or 10 μm, bond pads are preferred to increase the connectivity between layers. A 3D-AFPGA mockup test structure was then proposed for completing development and exercising the 3D integration process flows. This mockup test structure consists of a three-tier demonstration vehicle consisting of a chip-to-wafer and a subsequent chip-to-chip bond. Besides, an alternate copper bonding approach using pillars was explored. Although the intended application is for the 3D integration process compatible with the 3D AFPGA design, the test structure was also designed to be generally applicable to various applications for 3D integration. Because of the importance of thermal management of 3D-AFPGA, it is important to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and the 3D temperature distribution in the 3D-AFPGA are developed and discussed as well.

In the aeronautical field, the electronic integration roadmaps show that the weight and the volume dedicated to on-board electronics must be reduced by a factor of 4 to 10 compared to the existing ones for the most recurrent functions in the next years. This work is an opening to new technological solutions to increase our ability to save space while improving the overall reliability of the system. The first part of this work is dedicated to the study of “system in package” (SiP) solutions based on different substrates, namely organic or silicon. Generally speaking a SIP is composed by several active and passive components stacked on an interposer. Benchmarks done by our laboratory have demonstrated that in terms of substrate, embedded die technology leads to several advantages compared to 3D TSV or TGV based packaging approaches. The benefits provided by this substrate is the possibility to embed some surface mount technologies (SMT), some bare chips or some integrated passives devices (IPD) banks directly above or below the stacked active components. This way, top and bottom surface of the substrate can be used to integrate several heterogeneous dies side by side while using low profile flip-chip assemblies on the C4 side. Finally, in this kind of 3D architecture, this embedded technology enable a gain of integration, without using costly TSV connections. Substrates of high quality allow a reduction of I/Os interconnection pitches leading to very aggressive integration down to 50μm. Secondly, a 3D stack with 3 levels of components, as described above, leads to 2 or 3 REACH compliant sequential assembly processes, depending of the needs. In order to consider all the solutions for an optimized overall integration with high reliability, this work focuse on the study one simple SIP which includes the top die assembled by flip-chip. For the flip chip hybridization on organic interposers copper pillars technologies will be studied. The objective is to understand in depth the processes and to obtain information on the reliability aspect after thermal cycling stress of the flip chip assembly. Thirdly, we built many silicon test chips with different characteristics with a dedicated daisy chain test vehicle. The different parameters are: chip's thicknesses (50 to 200 μm), chip's sizes (2 to 8 mm), bump structures (diameter), the pitches of the interconnection (from 50 to 250 μm) and the number of interconnection rows. Designs were chosen in order to fit real operational configurations. Moreover, these configurations are interesting to build a comprehensive model in order to understand the failure mechanisms. These chips are then stacked by flip chip on the silicon and on the organic substrate. We are also designing the both configurations of substrates. Only the production of the organics part is outsourced. Fourth, for all assemblies thermos-cycling test results will be evaluated with thermo mechanical simulations done by finite elements. 3D models will take into account the different geometries in order to understand and quantify the various key parameters. The analysis will mainly focus on 3D interconnections. Design rules based on the results will be derivated. The aim is to obtain dimensional criteria based on stress versus deformation responses. Lastly intermetallic formation will be evaluated using EBSD analysis to obtain better understanding of copper pillar failures for this specific bumps size. Issued information's will be exploited for designing the future functional SIP. The ultimate goal of this work is finally to define mechanical design rules that can then be used in functional SiP modules.

The low-k/ultralow-k (LK/ULK) dielectric materials are introduced in the back-end of line (BEOL) to reduce the R-C delay in a chip with 40 nm technology node and beyond. The chips are generally packaged using a flip-chip technology, in which copper pillars are electrical connections and mechanical supports. Owing to the thermal mismatch between materials, copper pillars are sheared and higher stresses arise near the roots of the copper pillars, which causes cracks in LK/ULK materials that are porous and fragile in mechanics. In this study a rapid mechanical shear test of a copper pillar was proposed to mimic the corresponding shear force due to a temperature drop by finite element analysis (FEA) and bump shear experiments. FEA results for shear tests are in compliance with that of experiments and the high stress regions are conformed to the failure locations in the BEOL. Using the verified finite element models, a linear relationship between the shear force, the shear height and the temperature differential was built by keeping a bump in a same shear impact, which is valid for the temperature differential within 120 °C. In the suitable temperature range a mechanical shear test can quickly assess the failure possibility of LK/ULK materials caused by a temperature differential for evaluating their reliability in BEOL of an advanced chip.

In this paper, finite element simulations are used to analyze the plastic deformation of the solder ball and its stress and strain distributions. The bonding forces that depend on the forming temperature are investigated. The contact areas between the solder ball and the copper trace are also discussed. The largest contact area is regarded as the optimization condition during the thermal compression bonding processes. The effects of different pillar-trace shift ratios on the contact areas are also discussed to provide a guideline for avoiding product failure. Finally, an empirical equation adopting a four-parameter logistic nonlinear regression model for the pillar-trace gap in terms of the forming temperature and bonding forces is established.

Copper pillar micro bump is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking and high-density electronic components. In this study, Cu–Cu direct thermo-compression bonding (TCB) and anisotropic conductive paste (ACP) bonding methods are proposed for O 100 µm Cu-pillar bumped flip-chips. The process parameters including bonding temperature, bonding pressure and time are verified by die shear test and SEM/EDX cross-sectional analysis. The optimal bonding condition for TCB with regards to bonding pressure was defined to be 0.5N/bump at 300 °C or 0.3N/bump at 360 °C. In the case of ACP bonding, the minimum bonding pressure was about 0.3N/bump for gaining a seamless bonding interface.

With the rapid growth of the microelectronic packaging market, it is necessary to increase the throughput and reduce the cost of flip chip. Driven by these evolutions, a novel revolving-turret chip transferring (RTCT) technology is introduced to implement high-throughput flip chip packaging. The unnecessary time delays of packaging processes could be eliminated in the RTCT technology due to its parallel manner of motions. In order to analyze the packaging efficiency, the layout and movement sequence of the packaging system are studied, and a calculation model of packaging efficiency is proposed. Furthermore, the effects of the critical parameters (the horizontal and the vertical spacing of antennas and the maximum velocity and acceleration of the turret-type head) on packaging efficiency are investigated to search out the optimal parameters combination. To verify the performance of the RTCT technology under optimal parameters combination, two cases are implemented and compared. The results show that due to parallel motions of processes, unnecessary delays affecting the packaging efficiency have been reduced, and the packaging efficiency of ALN-9714 inlay could be more than 35k chips per hour. In addition, compared with the conventional flip chip packaging process, the RTCT technology is more effective in packaging the chips on antennas with multicolumn layout and small horizontal spacing.

Thermal cooling of solder bumps using Under Bump Metalization (UBM) with isotropic undercuts can result in an increase in stress concentration. The stress concentration on the passivation layers can result in cracking, especially when there are surface defects. Opportunities in reducing thermal stress depend on the type of passivation layer design as well as other factors. In Part I of this series of papers, the focus is on optimizing the thickness of the standard passivation design. In the standard passivation layer design, dielectrics would conformally cover the top metalization through two series of Chemical Vapor Deposition (CVD) coatings. Change in thickness for the two passivation layers' thickness using Finite Element Analysis (FEA) techniques combined with statistical Design of Experiments (DOE) allowed optimization of these layer thicknesses which brought about minimal stress on the passivation.

The first part of this work is dedicated to the study of “system in package” (SiP) solutions based on different substrates, namely organic or silicon. Generally speaking a SIP is composed by several active and passive components stacked on an interposer. Benchmarks done by Safran have demonstrated that in terms of substrate, embedded die technology leads to several advantages compared to 3D TSV or TGV based packaging approaches. The benefits leaded by this substrate is the possibility to embed some Surface Mount Technologies, bare chips or integrated passives devices (IPD) banks directly above or below the stacked active components. This way, top and bottom surface of the substrate can be used to integrate several heterogeneous dies side by side while using low profile flip-chip assemblies on the C4 side. Finally, in this kind of 3D architecture, this embedded technology enable a gain of integration, without using costly TSV connections. Substrates of high quality allow a reduction of interconnection pitches leading to very aggressive integration. Secondly, a 3D stack with 3 levels of components, as described above, means to, at least, 2 or 3 REACH compliant sequential assembly processes, depending on the needs. In order to consider all the solutions for an optimized integration and a high reliability, this work focused on the study of a simple SIP, which includes the top die assembled by flip-chip. For the flip chip hybridization, copper-pillars technologies are studied in the case of both organic and silicon interposers. The aim of this study is to understand in depth both processes and to obtain information on the reliability aspect after thermal cycling stress of the flip chip assembly. Thirdly, we built many silicon test chips with different characteristics with a dedicated daisy chain test vehicle. The different parameters are: chips' thicknesses (50 to 200 μm), chips' sizes (2 to 8 mm), bump structures (diameter), and the pitches of the interconnection (from 50 to 250 μm) and the number of interconnection rows. Designs were chosen in order to fit real operational configurations. Moreover, these configurations are interesting to build a comprehensive model in order to understand the failure mechanisms. These chips are then stacked by flip-chip on the silicon and on the organic substrate. We are also designing the two configurations of substrates. Only the production of the organics part is outsourced. Fourth, with all these configurations we will be able to fit the thermo-cycling test results with thermos-mechanical simulations done by finite elements. 3D models will take into account the different geometries in order to understand and quantify the various key parameters. The analysis will mainly focus on 3D interconnections. Design rules based on the results will be derivate. The aim is to obtain dimensional criteria based on stress versus deformation responses. Information obtained will be exploited for designing the future functional SIP. Fifth, in order to assess the electrical behaviors of this 3D architecture, signal integrity aspect will be considered as well. As for the design, the migration from an existing 2D electrical design to a 3D architecture design will be studied keeping the signal transmission without any degradation. The ultimate aim of this work is to define mechanical and electrical design rules that can then be used in functional SiP modules.

Photolithography has long been the key patterning technology for structuring organic materials used in advanced packaging applications like flip-chip wafer bumping, electroplated gold, solder bumps, copper pillar technologies and redistribution layers. Photolithography is a key manufacturing process and cost contributor, the careful selection of the right exposure solution is critical to achieve the best possible cost structure in today's industrial lithography applications We will introduce a projection exposure technology that uses a 1:1 projection lens; the projection exposure technology provides high resolution patterning performance. With the capability of varying NA from 0.07 to 0.14, a large depth of focus is obtained, that is required to ensure high pattern fidelity when working with thick resists. The projection exposure can also be applied to FOWLP applications, when the die placement data is fed into a software optimization algorithm to correct for it. We will present the projection exposure technology capability in managing the die placement error for FOWLP. In addition, details on the overlay capability of the projection exposure in thin resist are described and a Cost-of-Ownership comparison between different photolithography solutions is discussed.

Flip chip technology has made significant improvements to LED chip on board (COB) packages and modules by reducing thermal resistance compared with traditional wire bonded LEDs. However, one of the critical issues of flip chip packaged LEDs is the reliability of their solder interconnects, which are responsible for the heat transfer to the substrate. Based on a supply switching test, also called power cycle test, a model for monitoring and reliability was done to describe the remaining lifetime and additional the solder fatigue. Therefore, changes in thermal resistance of the LED-module were measured and correlated with solder fatigue of the LED flip chip package. Thermal impedance measurements were performed to monitor the status of the LED-module. Detailed analyses, comparing with the initial state, allow the evaluation of the occurring temperature swing of each LED chip. Single chip analysis combined with a thermal resistance driven monitoring model allows the calculation of remaining lifetime at each time during testing and beyond the first chip failure in a multi chip LED-module. Accordingly, it could be shown that the thermal impedance is a powerful tool for reliability monitoring and failure analysis.

Flip chip thermo-compression bonding (TCB) involves the use of heat and pressure to simultaneously form interconnections for microelectronic packaging. In-situ measurements of thermo-mechanical stresses that arise during this bonding process could provide unique insight to help better understand the TCB process. A 4 mm × 3 mm × 500 μm complementary metal-oxide-semiconductor (CMOS) sensor chip with an 8 × 8 array of Au-bumped sensor pads was developed for this purpose. It was designed to record XYZ force and temperature signals from bump locations, during a simulated flip chip process similar to TCB. In-situ measurements during simulated TCB events proved useful for tilt detection, thermal gradient characterization, and thermal expansion measurements. Further interpretation of the signals proved tilt and other thermo-mechanical effects were induced by thermal expansion mismatches. The most thermo-mechanically stressful stage of bonding was found to occur during thermal transients, specifically during bond head ramping. Further analysis concluded the actual time necessary to heat the bumps was less than 0.5 s. Finally, the lateral thermal gradient across the sensor chip was calculated to be smallest in the central bump locations, and largest in the bump array corners due to warpage, tilt, and heat sink effects of the digital logic region.

Electroless Ni/electroless Pd/immersion Au (ENEPIG) constitutes a promising metallization to replace the conventional ENIG or Ni/Au for 3D IC integrated module and optoelectronic packaging. Different ENEPIG plating thicknesses with copper pillar solder joints are subjected to thermal aging at 150 °C to investigate the intermetallic compounds (IMCs) formation and growth. Due to low temperature solid-state bonding, both Pd and Au layers do not completely diffused into Sn matrix and participated in the interfacial reactions to form (Pd,Au)Sn4 IMCs phase. (Pd,Au)Sn4 IMCs based on PdSn4 phase with dissolved Au, exhibits high growth rate and substantial consumption of Sn from solder. Upon increasing the aging time, it is found that (Cu,Ni)6Sn5 IMCs and (Pd,Cu,Au)Sn4 phase form at interface and follows a diffusion control mechanism, which weakened the solder joint and caused brittle fracture in a die peel test. (Cu,Ni)6Sn5 IMCs growth rate increases with decreases Pd thickness. Therefore, the types of IMCs formation, growth rate, and reliability of Cu pillar joint strongly depend on bonding temperature, Au and Pd thicknesses, and solder volume. Based on this study, the authors recommend suitable ranges of Au and Pd layer thicknesses for reliable Cu pillar solder joints.

Consumer demand for mobile services is expected to grow with the continued proliferation of connected devices including smartphones, wearables, and Internet of things. As a result, high-performance computing systems that support the core network and cloud infrastructures for these connected devices require unprecedented die-to-die bandwidth at low latency. To achieve next-generation performance requirements and to apply to commercial products, fundamental parameters for 2.5-D interposers are considered including: 1) high interconnect density at short interconnect length; 2) low power consumption; and 3) low packaging cost. The 2.5-D glass interposer described in this paper is superior to silicon interposer in cost and electrical performance, and to organic interposer in interconnect density. This paper describes a 2.5-D glass interposer as a ball grid array (BGA) package to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic interposers. Due to its high modulus and excellent surface finish, glass affords ultrafine line lithography to form high-density interconnects comparable to silicon, and the process described in this paper goes beyond silicon back-end-of-line processes by implementing a double-side semi-additive process (SAP) at increased copper layer thickness. This thicker metallization results in reduced conductor losses and improved bandwidth per channel compared to silicon. In addition, the low loss tangent of glass reduces dielectric losses in nets requiring through vias including clock distribution and high-speed off-package signals. Availability of glass in thin panel as well as in roll-to-roll formats beyond 500 mm in size reduces packaging cost compared to 300-mm wafer silicon interposer. The focus of this paper is on the integration of three enabling technologies: 1) advanced SAP for high-density redistribution layers (RDLs); 2) excimer laser ablation of RDL vias; and 3) fine-pitch thermocompression bonding with copper pillar die assembly—for a 2.5-D glass interposer at interconnect densities comparable to that of silicon to achieve terabit per second interdie bandwidth at highest BWF.

Advanced packaging technologies require materials which will allow for better resolution of patterns associated with the ever more challenging device architecture, along with materials that will allow for higher throughput. Device throughput can be increased with imaging materials that have higher sensitivity and metallization chemistries with faster electrodeposition rates. Chemically amplified photoresists offer the advantages of excellent sensitivity and resolution with good process margins, coupled with excellent stripping performance and plating bath compatibility for the film thicknesses that are required in packaging applications. Electrolytic copper plating products with fast deposition rates are a key factor in decreasing wafer plating time and increasing throughput. However, it is the integration of the photoimaging material and the subsequent plating chemistry that is essential in producing metallized structures for copper pillar and solder applications. Because the profile of the resist image is directly transferred during the electroplating process, it is critical to have a well formed image that is resistant to the plating chemistry. Plating bath contamination and resist strippability are other key factors in producing void-free, defect-free structures. Dow's newly introduced chemically amplified material is capable of film thicknesses from 30um to 80um by a single coating process with good uniformity. Imaging and process latitude are demonstrated at 40um and 65um thicknesses with emphasis on sidewall profiles and sensitivity. Further, the photoresist compatibility with INTERVIA™ Cu 8540 Electroplating Copper Chemistry is shown, along with NIKAL™ BP Ni plating chemistry and SOLDERON™ BP TS 6000 SnAg plating chemistry compatibility. The improvements in product line from Dow's INTERVIA™ Cu 8540 to INTERVIA™ 9000 Electroplating Copper Chemistry is also demonstrated in the paper, with thickness uniformity, high plating speed, and tunable morphology highlighted for various applications. The power of integration has enabled the development of this suite of products designed for compatibility and superior performance for advanced packaging technologies. ™ Trademark of The Dow Chemical Company

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.