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Die Placement Error management for Fan out Applications using Projection Lithography

Authors :
Markus Arendt
Habib Hichri
Mo Abdol
Source :
International Symposium on Microelectronics. 2017:000497-000501
Publication Year :
2017
Publisher :
IMAPS - International Microelectronics Assembly and Packaging Society, 2017.

Abstract

Photolithography has long been the key patterning technology for structuring organic materials used in advanced packaging applications like flip-chip wafer bumping, electroplated gold, solder bumps, copper pillar technologies and redistribution layers. Photolithography is a key manufacturing process and cost contributor, the careful selection of the right exposure solution is critical to achieve the best possible cost structure in today's industrial lithography applications We will introduce a projection exposure technology that uses a 1:1 projection lens; the projection exposure technology provides high resolution patterning performance. With the capability of varying NA from 0.07 to 0.14, a large depth of focus is obtained, that is required to ensure high pattern fidelity when working with thick resists. The projection exposure can also be applied to FOWLP applications, when the die placement data is fed into a software optimization algorithm to correct for it. We will present the projection exposure technology capability in managing the die placement error for FOWLP. In addition, details on the overlay capability of the projection exposure in thin resist are described and a Cost-of-Ownership comparison between different photolithography solutions is discussed.

Details

ISSN :
23804505
Volume :
2017
Database :
OpenAIRE
Journal :
International Symposium on Microelectronics
Accession number :
edsair.doi...........1537976ac468488c7755c53da4655919
Full Text :
https://doi.org/10.4071/isom-2017-tha13_010